.. Les-points-À-améliorer, 187 Les axes de recherche qui restent à explorer, p.187

D. Allen, A 0.2µm 1.8V SOI 550MHz 64b PowerPC Microprocessor with Copper Interconnects, International Solid-State Circuits Conference, pp.438-439, 1999.
URL : https://hal.archives-ouvertes.fr/in2p3-00084056

C. J. Alpert, A. Devgan, and S. T. Quay, Buffer Insertion for Noise and Delay Optimization, DAC, pp.362-367, 1998.
DOI : 10.1145/277044.277145

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

F. Assaderaghi, A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation, Proceedings of 1994 IEEE International Electron Devices Meeting, 1994.
DOI : 10.1109/IEDM.1994.383301

B. Austin, K. Bowman, X. Tang, and J. D. , A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI), Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372), pp.125-129, 1998.
DOI : 10.1109/ASIC.1998.722816

L. Benini, Saving power by synthesizing gated clocks for sequential circuits, IEEE Design & Test of Computers, vol.11, issue.4, pp.32-41, 1994.
DOI : 10.1109/54.329451

K. Bernstein and N. J. Rohrer, SOI Circuit Design Concepts, 2000.

T. Blalock and R. Jaeger, A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier, IEEE Journal of Solid-State Circuits, vol.27, issue.4, 1992.

K. Bowman, B. Austin, J. Eble, X. Tang, and J. D. , A Physical Alpha- Power Law MOSFET Model, IEEE Journal of Solid-States Circuits, vol.34, 1999.
DOI : 10.1109/lpe.1999.799442

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

I. Buchmann and M. Peterson, What's the best battery?," www.batteryuniversity.com/partone- 3.htmUltra Low Power CMOS Technology, NASA VLSI Design Symposium, 1991.

J. Burr and J. Shott, A 200mV Self-Testing Encoder/Decoder Using Stanford Ultra-Low-Power CMOS, International Solid-State Circuits Conference, pp.84-85, 1994.
DOI : 10.1109/isscc.1994.344717

M. R. Casu, Synthesis of low-leakage PD-SOI circuits with body-biasing, Proceedings of the 2001 international symposium on Low power electronics and design , ISLPED '01, pp.287-290, 2001.
DOI : 10.1145/383082.383170

A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design, 1995.
DOI : 10.1007/978-1-4615-2325-3

K. M. Chu and D. L. Pulfrey, A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic, IEEE Journal of Solid-State Circuits, vol.22, issue.4, pp.528-532, 1987.
DOI : 10.1109/JSSC.1987.1052767

L. Dadda, Some schemes for parallel multipliers, Alta Freq, pp.349-356, 1965.
DOI : 10.1109/arith.1983.6158074

W. Dally and J. Poulton, Digital Systems Engineering, 1998.
DOI : 10.1017/CBO9781139166980

K. Das and R. Brown, Ultra Low-Leakage Power Strategies for Sub- 1V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology, Proc. of the 16 th International Conference on VLSI Design, 2003.
DOI : 10.1109/icvd.2003.1183152

T. Dhaene and D. Zutter, Selection of lumped element models for coupled lossy transmission lines, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.11, issue.7, pp.805-815, 1992.
DOI : 10.1109/43.144845

I. and B. Dhaou, Low-Power Design Techniques for Deep Submicron Technology with Application to Wireless Transceiver Design, PhD Dissertation Royal Institute of Technology, 2002.

S. Dhar and M. Franklin, Optimum buffer circuits for driving long uniform lines, IEEE Journal of Solid-State Circuits, vol.26, issue.1, pp.32-40, 1991.
DOI : 10.1109/4.65707

T. Douseki, A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate, International Solid-State Circuits Conference, pp.84-85, 1996.

W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, vol.19, issue.1, pp.55-63, 1948.
DOI : 10.1063/1.1697872

C. C. Enz, F. Krummenacher, and E. A. Vittoz, An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low- Current Applications, Special Issue Analog Integrated Circuits and Signal Processing J. Low-Voltage and Low-Power Design, pp.83-114, 1995.

R. Frier, Minimizing Energy Dissipation in High-Speed Multipliers, International Symposium on Low Power Electronics and Design, pp.214-219, 1997.

G. Gerosa, A 2.2 W, 80 MHz superscalar RISC microprocessor, IEEE Journal of Solid-State Circuits, vol.29, issue.12, pp.1440-1452, 1994.
DOI : 10.1109/4.340417

L. P. Van-ginneken, Buffer placement in distributed RC-tree networks for minimal Elmore delay, IEEE International Symposium on Circuits and Systems, pp.865-868, 1990.
DOI : 10.1109/ISCAS.1990.112223

R. Gonzalez, B. Gordon, and M. Horowitz, Supply and threshold voltage scaling for low power CMOS, IEEE Journal of Solid-State Circuits, vol.32, issue.8, pp.1210-1216, 1997.
DOI : 10.1109/4.604077

J. Goswami and A. Chan, Fundamentals of Wavelets: Theory, Algorithms and Applications, Wiley Series in Microwave and Optical Engineering, 1999.
DOI : 10.1002/9780470926994

S. H. Gunther, F. Binns, D. Carmean, and J. C. Hall, Managing the impact of increasing microprocessor power consumption, Proc. Intel Technology Journal, 2000.

T. Han and D. A. Carlson, Fast area-efficient VLSI adders, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH), pp.49-56, 1987.
DOI : 10.1109/ARITH.1987.6158699

T. Hashimoto, A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications, IEEE Journal of Solid-State Circuits, vol.37, issue.11, pp.1574-1581, 2002.
DOI : 10.1109/JSSC.2002.803932

K. Hass, J. Venbrux, and P. Bhatia, Logic design considerations for 0.5-volt CMOS, Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001, 2001.
DOI : 10.1109/ARVLSI.2001.915552

N. Hedenstierna and K. O. Jeppson, Comments on the optimum CMOS tapered buffer problem, IEEE Journal of Solid-State Circuits, vol.29, issue.2, pp.155-159, 1994.
DOI : 10.1109/4.272124

J. Heer, Ultra Low Power special sessionCascode voltage switch logic: A differential CMOS logic family, IEEE International Solid-State Circuits Conference, pp.16-17, 1984.

J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 1996.

M. Horiguchi, T. Sakata, and K. Itoh, Switched Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's, IEEE Journal of Solid- States Circuits, vol.28, 1993.
DOI : 10.1109/vlsic.1993.920533

B. Hubbard, Ondes et ondelettes, Collection Sciences d'Avenir, Pour la science, 1995.

]. Y. Isma99, E. Ismail, J. Friedman, and . Neves, Figures of Merit to Characterize the Importance of On-Chip Inductance, IEEE Trans. VLSI Syst, vol.7, pp.442-449, 1999.

]. R. Jaeg75 and . Jaeger, Comments on 'An Optimized Output Stage for MOS Integrated Circuits, IEEE Journal of Solid-State Circuits, issue.3, pp.185-186, 1975.

A. Kanuma, CMOS circuit optimization, Solid-State Electronics, vol.26, issue.1, pp.47-58, 1983.
DOI : 10.1016/0038-1101(83)90160-0

A. Katoch, E. Seevinck, and H. Veendrick, Fast Signal Propagation for Point to Point On-Chip Long Interconnects using Current Sensing, European Solid-State Circuits Conference, 2002.

A. Keshavarzi, K. Roy, and C. Hawkins, Intrinsic leakage in low power deep submicron CMOS ICs, Proceedings International Test Conference 1997, p.146, 1997.
DOI : 10.1109/TEST.1997.639607

P. Kogge and H. Stone, A Parallel Algorithm for the Efficient Solution of a General Class of Recurrent Solutions, IEEE Trans. Computers, vol.22, issue.8, pp.786-793, 1973.

T. Kuroda, A 0.9V, 150MHz, 10mW, 4mm², 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme, IEEE Journal of Solid-State Circuits, pp.1770-1779, 1996.
URL : https://hal.archives-ouvertes.fr/in2p3-00021287

M. Lakshmanan, M. Othman, and . Ali, High performance parallel multiplier using Wallace-Booth algorithm, ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575), pp.433-436, 2002.
DOI : 10.1109/SMELEC.2002.1217859

L. Lev and P. Chao, Down to the Wire: Requirements for Nanometer Design Implementation Cadence White Papers, http://www.cadence.com/whitepapers/4064_NanometerWP_fnlv2, CMOS Tapered Buffer IEEE Journal of Solid-State Circuits, vol.25, issue.4, pp.1005-1008, 1990.

M. Liao, C. Su, C. Chang, and A. Wu, A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), pp.81-84, 2002.
DOI : 10.1109/ISCAS.2002.1009782

J. Lillis, C. Cheng, and T. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, IEEE Journal of Solid-State Circuits, vol.31, issue.3, pp.437-447, 1996.
DOI : 10.1109/4.494206

H. C. Lin and L. W. Linholm, An Optimized Output Stage for MOS Integrated Circuits, IEEE Journal of Solid-State Circuits, vol.10, issue.2, pp.106-109, 1975.

P. Macken, A voltage reduction technique for digital systems, 1990 37th IEEE International Conference on Solid-State Circuits, pp.238-239, 1990.
DOI : 10.1109/ISSCC.1990.110213

A. Maheshwari and W. Burleson, Current Sensing for Global Interconnects, Secondary Design Issues: Analysis and Solutions, IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, 2001.

S. Mallat, A Theory for Multiresolution Signal Decomposition: The Wavelet Representation, IEEE Trans. On Pattern Analysis and Machine Intelligence, vol.11, issue.7, 1989.

P. Meier, R. Rutenbar, and R. Carley, Exploring multiplier architecture and layout for low power, Proceedings of Custom Integrated Circuits Conference, 1996.
DOI : 10.1109/CICC.1996.510609

E. Gordon and . Moore, Cramming More Components Onto Integrated Circuits, Electronics, vol.38, 1965.

. Shin-'ichiro-mutoh, 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS, IEEE Journal of Solid-State Circuits, vol.30, issue.8, pp.847-854, 1995.
DOI : 10.1109/4.400426

S. Narendra, Scaling of stack effect and its application for leakage reduction, Proceedings of the 2001 international symposium on Low power electronics and design , ISLPED '01, pp.195-200, 2001.
DOI : 10.1145/383082.383132

G. Vojin and . Oklobdzija, The Computer Engineering Handbook, pp.2-54, 2002.

C. Piguet, Low-power design of 8-b embedded CoolRisc microcontroller cores, IEEE Journal of Solid-State Circuits, vol.32, issue.7, pp.1067-1078, 1997.
DOI : 10.1109/4.597297

J. M. Rabaey, Digital Integrated Circuits: A Design Perspective, 1996.

D. Radhakrishnan, S. R. Whitaker, and G. K. Maki, Formal design procedures for pass transistor switching circuits, IEEE Journal of Solid-State Circuits, vol.20, issue.2, pp.531-536, 1985.
DOI : 10.1109/JSSC.1985.1052339

]. R. Roge96, H. Rogenmoser, N. Kaeslin, and . Felber, The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Circuits, CA381507?stt=000& industryid=2 Proc. 22 nd European Solid-State Circuits Conference, pp.124-127, 1996.

E. Rydgren, T. Ea, F. Amiel, F. Rossant, and A. Amara, IRIS features extraction using wavelet packets, 2004 International Conference on Image Processing, 2004. ICIP '04., 2004.
DOI : 10.1109/ICIP.2004.1419435

E. Seevinck, S. Member, P. J. Ieee, H. Van-beers, and . Ontrop, Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's, IEEE Journal of Solid-State Circuits, vol.26, issue.4, 1991.
DOI : 10.1109/4.75050

T. Sakurai, Approximation of wiring delay in MOSFET LSI, SC-18, pp.418-426, 1983.
DOI : 10.1109/JSSC.1983.1051966

T. Sakurai and R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE Journal of Solid-State Circuits, vol.25, issue.2, 1990.
DOI : 10.1109/4.52187

G. Shahidi, Partially-depleted SOI technology for digital logic, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999.
DOI : 10.1109/ISSCC.1999.759337

N. Shibata, Current Sense Amplifiers for Low-Voltage Memories, IEICE Trans. Electron, issue.8, 1996.

H. Soeleman, Robust ultra-low power sub-threshold DTMOS logic, Proceedings of the 2000 international symposium on Low power electronics and design , ISLPED '00, 2000.
DOI : 10.1145/344166.344187

V. Stojanovic and V. Oklobdzija, Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems, IEEE Journal of Solid-State Circuits, vol.34, issue.4, pp.536-548, 1999.
DOI : 10.1109/4.753687

J. M. Stork, Technology Leverage for Ultra-Low Power Information Systems, IEEE Symposium on Low Power Electronics, pp.52-55, 1994.
DOI : 10.1109/lpe.1994.573200

M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu et al., A 1.5-ns 32-b CMOS ALU in double pass-transistor logic, IEEE Journal of Solid-State Circuits, vol.28, issue.11, pp.1145-1151, 1993.
DOI : 10.1109/4.245595

URL : https://hal.archives-ouvertes.fr/in2p3-00420482

R. M. Swanson and J. D. , Ion-implanted complementary MOS transistors in low-voltage circuits, IEEE Journal of Solid-State Circuits, vol.7, issue.2, pp.146-153, 1972.
DOI : 10.1109/JSSC.1972.1050260

S. M. Sze, S. H. Unger, and C. Tan, Physics of Semiconductor DevicesClocking Schemes for High-Speed Digital Systems, IEEE Trans. Comput, pp.35-880, 1981.

H. Varadarajan, Low-Power Design Issues, The Computer Engineering Handbook, 2002.

S. R. Vemuru and A. R. Thorbjornsen, Variable-taper CMOS buffers, IEEE Journal of Solid-State Circuits, vol.26, issue.9, pp.1265-1269, 1991.
DOI : 10.1109/4.84943

C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, vol.13, issue.1, pp.14-17, 1964.
DOI : 10.1109/PGEC.1964.263830

B. Wicht, Current Sense Amplifiers for Embedded SRAM in High- Performance System-on-a-Chip Designs, 2003.

K. Yano, Y. Sasaki, K. Rikino, and K. Seki, Top-down pass-transistor logic design, IEEE Journal of Solid-State Circuits, vol.31, issue.6, pp.792-803, 1996.
DOI : 10.1109/4.509865

J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE Journal of Solid-State Circuits, vol.24, issue.1, pp.62-70, 1989.
DOI : 10.1109/4.16303

Y. Zhu, T. Tan, and Y. Wang, Biometric Personal Identification Based on Iris Patterns, International Conference on Pattern Recognition, 2000.

. Publications-associées-À, Modeling Subthreshold SOI Logic for Static Timing Analysis Alexandre Valentian, IEEE Transactions on VLSI, 2004.

P. Depleted, S. Menu, L. Low-power-applications, A. Hostis, P. Valentian et al., Ultra-Low-Voltage Robust Design Issues in Deep-Submicron CMOS On-Chip Signaling for Ultra Low-Voltage 0.13µm CMOS SOI Technology Alexandre Valentian Modélisation du délai d'une porte CMOS SOI en faible inversion An Accurate Estimation Model for Subthreshold CMOS SOI Logic, IEEE European Solid-State Circuit Conference, 2002.