Abstract : Recently the field of video, image and audio processing has experienced several significant progresses on both the algorithms and the architectures levels. One of these evolutions is the emergence of the new ISO/IEC JPEG2000 image compression standard which succeeds to JPEG. This new standard presents many functionalities and features which allows it to be adapted to a large spectrum of applications. However, these features bring up new algorithmic complexities of higher degree than those of JPEG which in turn makes it very difficult to be optimized for certain implementations under very hard constraints. Those constraints could be area, timing or power constraints or more likely all of them. One of the key steps during the JPEG2000 processing is entropy coding that takes about 70 % of the total execution time when compressing an image. It is therefore essential to analyze the potentialities of optimizations of implementations of JPEG2000. FPGA devices are currently the main reconfigurable circuits available on the market. Although they have been used for a long time only for ASIC prototyping, they are able today to provide an effective solution to the hardware implementation of applications in many fields. Considering the progress experienced by the FPGA semiconductor industry on integration capacity and working frequency, reconfigurable architectures are now an effective and competitive solution to meet the needs of both prototyping and final hardware implementations. In this work we propose a methodology for the study of the possibilities of implementation of JPEG2000. This study starts with the evaluation of software implementations on commercial platforms, and quickly extended through software optimizations based on specialized SIMD libraries exploiting fine grain concurrency. Following this first study we carried out a hardware implementation of an entropic dual-coder on FPGA which was used as a coprocessor on both a host machine and on an embedded industrial platform. After this implementation we evolved our approach to a system approach. In this last part we carried out hardware/software partitioning of the entropic coder on FPGA, then a multi-coder implementation was realized on FPGA and used like coprocessor on chip for the creation of a system on programmable chip. These various works allowed us to cover a large part of the applications space that JPEG2000 can target. At the same time these implementations give a global vision on the possibilities and limits of the implementations of JPEG2000. Furthermore this study is a support to decide architecture-application mapping for JPEG2000 implementation.