N. Transistor and .. État-de-forte-inversion, 203 A.10 Schéma de transistor avec capacités 204 A.11 Transistor NMOS en mode non saturé, p.210

D. La and D. , Application à la DPA Sommaire 8.1 Application à, p.132

.. Application-À-la-dpa-de-l-'aes, 136 8.2.1 Séparation des chiffrés et des évènements microélectroniques associés136 8.2.2 Schéma de la fonction

D. Application-À-la-variante-de-la, D. .. De-l-'aes, and .. Xor2, 139 8.3.1 Séparation des chiffrés et des évènements microélectroniques associés139 8.3.2 Schéma de la porte

.. Application-À-la-dpa-de-l-'aes-en-technologie-asynchrone, 142 8.4.1 Introduction, p.142

.. La-nécessité-d-'un-nouveau-codage-de-données, 156 9.4.1 Équilibrage par extension des réseaux de transistors, p.158

.. La-nécessité-d-'un-nouveau-protocole-de-données, 160 9.5.1 Nécessité d'un état électrique initial connu par extension des réseaux de transistors, p.160

.. Application-synchronisée, 184 10.2.2 Conception d'autres portes logiques synchrones, Testabilité, p.187

A. Annexe, M. Théorie-du-transistor, A. Sommaire, and M. Le-transistor, 196 A.2.1 L'inverseur

M. Le-transistor and .. , 201 A.3.1 Capacités du transistors

B. Sommaire, 1 Processus de fabrication des transistors NMOS et PMOS et modèles spice, p.214

C. Sommaire, T. , and D. , 220 C.2 Historique et fonctions fréquentes en cryptographie, p.230

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