.. Secured-crypto-processors-design, 49 3.1.1 Security target, p.49

A. Des-architecture-operating-in, I. , and .. , 50 3.2.2 DES datapath improvement thanks to a generalized pipelining 52 3.2.3 Optimal software / hardware partition to realize all DES variants, Comparison with other fast and versatile implementations of DES . . . . 63 3.2.6 Proposed architectures modifications for bit-slice, p.65

S. Des-remarkable and .. , 77 3.5.1 Semi-weak keys, p.84

H. Explanation, 90 3.6.1 Interpretation of the differential trace using Single versus multi-bit HW or HD selection functions Conclusion: improvement of side-channels analyzes, p.106

A. Strategy-for-secured-asics and .. , 128 4.3.1 Using differential logic to thwart 130 4.3.2 The " backend duplication " method 131 4.3.3 The constraints required by the " backend duplication " method Backend duplication " method insertion into an existing design flow . . . 133 4.3.5 Comparison of the " backend duplication " method with related works . . . 134 4.3.6 Suitability of the " backend duplication " method with some logic styles, ., p.139

B. Figure, 17: Date selected for the SNR computation while doing the DPA on DES sbox #8

E. Elliptic, C. Cryptography, and E. E. Attack, EMI ElectroMagnetic Interference FA Fault Attack FE First Encounter, backend design product of Cadence [47] FPGA Field Programmable Gate Arrays GNU Gnu is Not Unix, p.488

H. Hw-hamming-distance, Hamming Weight IC Integrated Circuit (typically an ASIC or an FPGA) IDE Integrated Development Environment IEEE, ieee.org/) IP Initial Permutation DES (Note that: IP ?1 . = FP) IP Intellectual Property (understand: " stand-alone hardware macro " ) Continued on next page

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