M. Horowitz and W. Dally, How scaling will change processor architecture, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), pp.174-190, 2004.
DOI : 10.1109/ISSCC.2004.1332629

. Fpoa, Available on : http://www.mathstar.com

. Xilinx, Available on : http://www.xilinx.com

A. Fin, F. Fummi, M. Martignano, and M. Signoretto, SystemC, Proceedings of the ninth international symposium on Hardware/software codesign , CODES '01, p.1722, 2001.
DOI : 10.1145/371636.371657

. Celoxica, Handel-c. Available on

R. K. Gupta, C. N. Coelho, and G. D. Micheli, Synthesis and simulation of digital systems containing interacting hardware and software components, Proc. of the DAC, 1992.

F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska et al., Hardware-software co-design of embedded systems : The polis approach, 1997.
DOI : 10.1007/978-1-4615-6127-9

R. Ernst, J. Henkel, and T. Benner, Hardware-software cosynthesis for microcontrollers, Design and Test of Computers, p.6475, 1993.

R. K. Brayton, A. Sangiovanni-vincentelli, A. Aziz, S. Cheng, S. Edwards et al., VIS, Proceedings of the Eighth International Conference on Computer Aided Verication CAV, 1996.
DOI : 10.1007/BFb0031812

A. Kalavade and E. A. Lee, A global criticality/local phase driven algorithm for theconstrained hardware/software partitioning problem, Proceedings of the Third International Workshop on Hardware/Software Codesign, p.4248, 1994.

A. Kalavade and P. A. Subrahmanyam, Hardware/software partitioning for multi-function systems, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, pp.516-521, 1997.
DOI : 10.1109/ICCAD.1997.643588

K. S. Chatha and R. Vemuri, MAGELLAN, Proceedings of the ninth international symposium on Hardware/software codesign , CODES '01, p.4247, 2001.
DOI : 10.1145/371636.371671

B. P. Dave, G. Lakshminarayana, and N. K. Jha, COSYN, Proceedings of the 34th annual conference on Design automation conference , DAC '97, p.703708, 1997.
DOI : 10.1145/266021.266341

W. Theodore, J. T. Manikas, and . Cain, Genetic algorithms and simulated annealing algorithm, Annual ACM IEEE Design Automation Conference, p.96101, 1996.

E. William and . Hart, A theoretical comparison of evolutionary algorithms and simulated annealing, proceedings of the Fifth Annual Conf. on Evolutionary Programming, 1996.

F. Glover, Future paths for integer programming and links to articial intelligence, Computers and Operation research, p.533549, 1986.

M. Laguna and F. Glover, Tabu search, 1997.

D. De-werra, A. Hertz, and E. Taillard, A tutorial on tabu search, Proc. of Giornate di Lavoro AIRO'95 (Enterprise Systems : Management of Technological and Organizational Changes), p.1324, 1995.

F. Glover, Tabu search, part i, ORSA Journal on Computing 2, 1989.

F. Glover, Tabu Search???Part II, ORSA Journal on Computing 2, 1990.
DOI : 10.1287/ijoc.2.1.4

M. Ehrgott and X. Gandibleux, Approximative solution methods for multiobjective combinatorial optimization, Top, vol.3, issue.1, p.188, 2004.
DOI : 10.1007/BF02578918

URL : https://hal.archives-ouvertes.fr/hal-00462043

J. H. Holland, K. E. De, and . Jong, Outline for a logical theory of adaptative systems An analysis of the behavior of a class of genetic adaptive systems, Journal of the association of computing machinery University of, 1962.

D. Goldberg, Genetic algorithms in search, optimization and machine learning, 1989.

J. E. Baker, Reduicing bias and ineciency in the selection algorithm, proceeding of the 2nd international conference on genetic algorithms, p.1421, 1987.

B. Sareni, Méthodes d'optimisation multimodales associées à la modélisation numérique en électromagnétisme, thèse de doctorat école centrale de, 1999.

E. Zitzler and L. Thiele, An evolutionary algorithm for multiobjective optimization : the strength pareto approach, TIK Report, 1998.

D. W. Corne, J. D. Knowles, and M. J. Oates, The Pareto Envelope-Based Selection Algorithm for Multiobjective Optimization, Proceedings of the Sixth International Conference on Parallel Problem Solving from Nature (PPSN VI), p.839848, 2000.
DOI : 10.1007/3-540-45356-3_82

K. Deb, S. Agrawal, A. Pratap, and T. Meyarivan, A Fast Elitist Non-dominated Sorting Genetic Algorithm for Multi-objective Optimization: NSGA-II, Proceedings of the Parallel Problem Solving from Nature VI (PPSN-VI), 2000.
DOI : 10.1007/3-540-45356-3_83

N. Srivinas and K. Deb, Multiobjective optimization using nondominated sorting in genetic algorithms, technical report, department of mechanical engineering, institute of technology India, 1993.

T. Givargis, F. Vahid, and J. Henkel, System-level exploration for pareto-optimal congurations in parameterized systems-on-chip, IEEE Transactions on VLSI Systems, p.416422, 2002.

T. Givargis and F. Vahid, Platune: a tuning framework for system-on-a-chip platforms, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, p.13171327, 2002.
DOI : 10.1109/TCAD.2002.804107

F. Vahid, T. Givargis, and J. Henkel, Evaluating power consumption of parameterized cache and bus architecture in system-on-a-chip designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001.

G. Ascia, V. Catania, and M. Palesi, A GA-Based Design Space Exploration Framework for Parameterized System-On-A-Chip Platforms, IEEE Transaction on Evolutionary Computation, p.329346, 2004.
DOI : 10.1109/TEVC.2004.826389

K. Ghali, Méthodologie de conception système à base de plateformes recongurables et programmables, Thèse Orsay, 2005.

E. Zitzler, K. Deb, and L. Thiele, Multiobjective evolutionnary algorithms : A comparative case study and the strength pareto approach, In IEEE Trans. On Evolutionary Computation, p.257271, 1999.

M. Ehrgott and X. Gandibleux, Approximative solution methods for multiobjective combinatorial optimization, SBCCI '05 : Proceedings of the 18th annual symposium on Integrated circuits and system design, p.188, 2004.
DOI : 10.1007/BF02578918

URL : https://hal.archives-ouvertes.fr/hal-00462043

S. Choi and C. Wu, Partitioning and allocation of objects in heterogeneous distributed environments using the niched pareto genetic algorithm, Proceedings of 1998 Asia Pacic Software Engineering Conference APSEC, pp.322-329, 1998.

K. B. Chehida, P. Guitton-ouhamou, S. Raimbault, and M. Auguin, A multiobjective hardware-software partitioner for dynamically recongurable system design, WSEAS Transactions on Systems, p.741745, 2003.

K. B. Chehida, S. Raimbault, and M. Auguin, Partitionnement logiciel matériel ciblant une architecture recongurable dynamiquement, Technique et Science Informatiques Architecture des ordinateurs, p.737757, 2003.

J. Diguet, G. Gogniat, J. Philippe, Y. Le-moullec, S. Bilavarn et al., Epicure : A partitioning and co-design framework for recongurable computing. Microprocessors and Microsystems, Special Issue on FPGA's, p.30367387, 2006.

P. Robert, N. K. Dick, and . Jha, Mogac : A multiobjective genetic algorithm for hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, p.920935, 1998.

C. Grecu, P. Pande, A. Ivanov, and R. Saleh, A scalable communicationcentric soc interconnect architecture, IEEE International Symposium on Quality Electronic Design, pp.343-348, 2004.

N. Thepayasuwan, S. Kallakuri, A. Doboli, and S. Doboli, Communication Subsystem Synthesis and Analysis Tool using Bus Architecture Generation and Stochastic Arbitration Policies, 2005 IEEE International Symposium on Circuits and Systems, pp.1044-1047, 2005.
DOI : 10.1109/ISCAS.2005.1464770

D. Shin, S. Abdi, and D. D. Gajski, Automatic generation of bus functional models from transaction level models, ASP-DAC '04 : Proceedings of the 2004 conference on Asia South Pacic design automation, p.756758, 2004.

M. Ariyamparambath, D. Bussaglia, B. Reinkemeier, T. Kogel, and T. Kempf, A highly ecient modeling style for heterogeneous bus architectures, International Symposium on System-on-Chip, p.8387, 2003.

. Altera, Available on : http://www.altera.com

. Xilinx, Xilinx microblaze soft core processor Available on

. Xilinx, Embedded developement kit Available on

D. Taubman and M. W. Marcellin, Jpeg2000 -image compression fundamentals, standards and practice, 2001.

R. Benmouhoub, I. Aouadi, and O. Hammami, System on programmable chip plateform based design of jpeg-2000 entropy coder, Workshop on synthesis and system integration of mixed information technologies (SASIMI'04), p.103106, 2004.

I. Aouadi, R. Benmouhoub, and O. Hammami, System on a programmable chip oriented JPEG-2000 entropy coder implementation for multimedia embedded systems, 2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE., 2005.
DOI : 10.1109/ICCE.2005.1429910

M. Antonini, M. Barlaud, P. Mathieu, and I. Daubechies, Image coding using wavelet transform, IEEE Transactions on Image Processing, p.205220, 1992.
DOI : 10.1109/83.136597

URL : https://hal.archives-ouvertes.fr/hal-01322224

M. J. Gormish, D. Lee, and M. W. Marcellin, JPEG 2000: overview, architecture, and applications, Proceedings 2000 International Conference on Image Processing (Cat. No.00CH37101), p.2932, 2000.
DOI : 10.1109/ICIP.2000.899217

D. , S. Cruz, and T. Ebrahimi, An analytical study of the jpeg2000 functionalities, Proc. IEEE Int. Conf. Image Processing ICIP, p.4952, 2000.

K. Ghali, O. Hammami, and I. Hermann, Multiobjective design of embedded processors on FPGA platforms, 24th International Conference on Distributed Computing Systems Workshops, 2004. Proceedings., p.871875, 2004.
DOI : 10.1109/ICDCSW.2004.1284135

D. Kulkarni, W. A. Najjar, R. Rinker, and F. J. Kurdahi, Compile-time area estimation for LUT-based FPGAs, ACM Transactions on Design Automation of Electronic Systems, vol.11, issue.1, p.104122, 2006.
DOI : 10.1145/1124713.1124721

P. Paulin, Emerging challenges for mpsoc platforms. MPSoC2006 (6th international forum on Application-Specic Multiprocessor SoC)

A. A. Jerraya, A. Bouchhima, and F. Pétrot, Programming models and HW-SW interfaces abstraction for multi-processor SoC, Proceedings of the 43rd annual conference on Design automation , DAC '06, p.280285, 2006.
DOI : 10.1145/1146909.1146981

URL : https://hal.archives-ouvertes.fr/hal-00103520

G. Martin, Overview of the MPSoC design challenge, Proceedings of the 43rd annual conference on Design automation , DAC '06, p.274279, 2006.
DOI : 10.1145/1146909.1146980

L. Xue, O. Ozturk, F. Li, M. Kandemir, and I. Kolcu, Dynamic partitioning of processing and memory resources in embedded MPSoC architectures, Proceedings of the Design Automation & Test in Europe Conference, p.261272, 2006.
DOI : 10.1109/DATE.2006.244044

M. D. Nava, P. Blouet, P. Teninge, M. Coppola, T. Ben-ismail et al., An open platform for developing multiprocessor SoCs, IEEE Computer, p.6067, 2005.
DOI : 10.1109/MC.2005.218

A. Grasset, F. Rousseau, and A. A. Jerraya, Network interface generation for mpsoc: from communication service requirements to rtl implementation, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004., p.6669, 2004.
DOI : 10.1109/IWRSP.2004.1311097

URL : https://hal.archives-ouvertes.fr/hal-00008038

W. O. Cesario, G. Nicolescu, L. Gauthier, D. Lyonnard, and A. A. Jerraya, Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design, Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001, p.110, 2001.
DOI : 10.1109/IWRSP.2001.933847

URL : https://hal.archives-ouvertes.fr/hal-00008079

M. P. Bonaciu, Plateforme exiblepour l'exploitation d'algorithmeset d'architectures en vue de la réalisation d'application vidéo haute dénition sur des architectures multiprocesseurs monopuce. Available on, 2006.

I. Petkov, Design of multiprocessor system on chip : Link between simulation and realization. Available on : http://www, TIMA.com, 2006.
URL : https://hal.archives-ouvertes.fr/tel-00011618

Y. Sheynin, E. Suvorova, and F. Shutenko, Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), p.6, 2006.
DOI : 10.1109/ISVLSI.2006.30

R. Ho, K. Mai, and M. Horowitz, The future of wires, PROCEEDINGS OF THE IEEE, p.490504, 2001.
DOI : 10.1109/5.920580

W. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), p.684689, 2001.
DOI : 10.1109/DAC.2001.935594

A. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00012749

P. Wielage and K. Goossens, Networks on silicon: blessing or nightmare?, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, p.196, 2002.
DOI : 10.1109/DSD.2002.1115369

J. Xu and W. Wolf, Networks and applications : Are application-specic networks worth the trouble ? Workshop on Future Interconnection and Network on Chip, 2006.

G. De, M. , and L. Benini, Networks on chips, 2006.

J. Henkel, W. Wolf, and S. Chakradhar, On-chip networks: a scalable, communication-centric embedded system design paradigm, 17th International Conference on VLSI Design. Proceedings., p.845851, 2004.
DOI : 10.1109/ICVD.2004.1261037

L. Benini and D. Bertozzi, Network-on-chip architectures and design methods, IEE Proceedings on Computers and Digital Techniques, p.261272, 2005.

L. M. Ni, Issues in designing truly scalable interconnection networks, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing ICPPW-96, p.7483, 1996.
DOI : 10.1109/ICPPW.1996.538592

X. Ningyi, L. Xianglun, L. Renfei, and Z. Zucheng, A SystemC-based NoC Simulation Framework supporting Heterogeneous Communicators, 2005 6th International Conference on ASIC, p.10321035, 2005.
DOI : 10.1109/ICASIC.2005.1611478

P. Wielage and K. Goossens, Networks on silicon: blessing or nightmare?, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, p.196200, 2002.
DOI : 10.1109/DSD.2002.1115369

P. Aldworth, System-on-a-chip bus architecture for embedded applications, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), p.297298, 1999.
DOI : 10.1109/ICCD.1999.808553

M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik et al., Addressing the system-on-a-chip interconnect woes through communication-based design, Proceedings of the 38th conference on Design automation , DAC '01, p.667672, 2001.
DOI : 10.1145/378239.379045

T. Bjerregaard and S. Mahadevan, A survey of research and practices of Network-on-chip, ACM Computing Surveys (CSUR) archive, 2006.
DOI : 10.1145/1132952.1132953

E. Rijpkema, Trade-os in the design of a router with both guaranteed and best-eort services for networks on chip, DATE conference, pp.350-355, 2003.

D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou et al., Noc synthesis ow for customized domain specic multiprocessor systems-on-chip, IEEE Transaction on Parallel and Distributed Systems, vol.16, p.113129, 2005.

D. Bertsekas and R. Gallager, Data networks, 1991.

J. Walrand and P. Varaiya, High-performance communication networks, 2000.

A. Laely, J. Liang, R. Tesseir, and W. Burleson, Adaptive system on a chip (asoc) : a backbone for power-aware signal processing cores, IEEE Proceedings of the International Conference on Image Processing, pp.105-108, 2003.

M. Millberg, E. Nilsson, R. Thid, S. Kumar, and A. Jantsch, The Nostrum backbone-a communication protocol stack for Networks on Chip, 17th International Conference on VLSI Design. Proceedings., pp.693-696, 2004.
DOI : 10.1109/ICVD.2004.1261005

F. Karim, A. Nguyen, and S. Dey, An interconnect architecture for networking systems on chips, IEEE Micro, vol.22, issue.5, p.3645, 2002.
DOI : 10.1109/MM.2002.1044298

T. Marescaux, A. Bartic, D. Verkest, S. Vernalde, and R. Lauwereins, Interconnection networks enable ne-grain dynamic multi-tasking on fpgas, Proceedings of the Recongurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.795805, 2002.

K. Goossens, J. Dielissen, and A. Radulescu, Aethereal network on chip : concepts, architectures, and implementations, IEEE proceedings International Symposium onSystem-on-Chip, p.414421, 2005.

E. Rijpkema, K. Goossens, and P. Awielage, Router architecture for networks on silicon, 2nd Workshop on Embedded Systems (PROGRESS), pp.181-188, 2001.

M. A. Forsell, A scalable high-performance computing solution for networks on chips, IEEE Micro, p.4655, 2002.
DOI : 10.1109/MM.2002.1044299

I. Saastamoinen, M. Alho, and J. Nurmi, Buer implementation for proteo networks-on-chip, IEEE International Symposium on Circuits and Systems, p.113116, 2003.

I. Saastamoinen, M. Alho, J. Pirttimäki, and J. Nurmi, Proteo interconnect ips for networks-on-chip, 2002.

D. Sigüenza-tortosa and J. Nurmi, Proteo : A new approach to network-onchip Socin : A parametric and scalable network-on-chip, IASTED International Conference on Communication Systems and Networks 16th Symposium on Integrated Circuits and Systems Design, p.169174, 2002.

D. Wiklund and D. Liu, SoCBUS: switched network on chip for hard real time embedded systems, Proceedings International Parallel and Distributed Processing Symposium, 2003.
DOI : 10.1109/IPDPS.2003.1213180

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS architecture and design process for network on chip, Euromicro : The Journal of Systems Architecture, Special Issue on Networks on Chip, pp.105-128, 2004.
DOI : 10.1016/j.sysarc.2003.07.004

M. Dall-'osso, G. Biccari, L. Giovannini, D. Bertozzi, and L. Benini, xpipes : a latency insensitive parameterized network-on-chip architecture for multiprocessor socs, ICCD '03 : Proceedings of the 21st International Conference on Computer Design, p.536539, 2003.

F. Moraes, N. Calazans, A. Mello, L. , and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, p.6993, 2004.
DOI : 10.1016/j.vlsi.2004.03.003

A. Mello, L. Tedesco, N. Calazans, and F. Moraes, Virtual channels in networks on chip, Proceedings of the 18th annual symposium on Integrated circuits and system design , SBCCI '05, p.178183, 2005.
DOI : 10.1145/1081081.1081128

T. Bjerregaard, S. Mahadevan, R. G. Olsen, and J. Sparso, An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip, 2005 International Symposium on System-on-Chip, p.171174, 2005.
DOI : 10.1109/ISSOC.2005.1595670

Y. Durand, C. Bernard, and D. Lattard, Faust : On-chip distributed soc architecture for a 4g baseband modem chipset, Proceedings Design and Reuse IP-SOC, p.5155, 2005.

N. Shah, W. Plishker, and K. Keutzer, NP-Click, 2nd Workshop on Network Processors (NP-2) at the 9th International Symposium on High Performance Computer Architecture (HPCA-9) Anaheim CA, 2003.
DOI : 10.1016/B978-012198157-0/50011-8

F. Cappello and D. Etiemble, MPI versus MPI+OpenMP on the IBM SP for the NAS Benchmarks, ACM/IEEE SC 2000 Conference (SC'00), 2000.
DOI : 10.1109/SC.2000.10001

S. K. Shukla and M. Theobald, Special issue on formal methods for globally asynchronous and locally synchronous (gals) systems. Form, Methods Syst

. Modelsim, Modelsim 6.0a se Available on

F. Ghenassia, Transaction-Level Modeling with SystemC TLM Concepts and Applications for Embedded Systems, 2005.

F. Fummi, S. Martini, G. Perbellini, and M. Poncino, Native ISS-SystemC integration for the co-simulation of multi-processor SoC, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1268905

K. Ghali and O. Hammami, Embedded processor characteristics specication through multiobjective evolutionary algorithms, IEEE International Symposium on Industrial Electronics, p.907912, 2003.

K. Ghali and O. Hammami, Embedded processors optimization with hardware in the loop, 2004 IEEE International Symposium on Industrial Electronics, pp.561-564, 2004.
DOI : 10.1109/ISIE.2004.1571868

S. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, Application-specic heterogeneous multiprocessor synthesis using extensible processors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, p.15891602, 2006.

K. Neal, S. S. Bambha, and . Bhattacharyya, Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors, IEEE Transactions on Parallel and Distributed Systems, vol.16, issue.2, 2005.

S. Pasricha and N. Dutt, COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC, Proceedings of the Design Automation & Test in Europe Conference, p.16, 2006.
DOI : 10.1109/DATE.2006.244066

D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, Automatic generation of application-specic architectures for heterogeneous multiprocessor system-onchip, DAC, p.518523, 2001.

F. Sun, N. K. Jha, S. Ravi, and A. Raghunathan, Synthesis of application-specic heterogeneous multiprocessor architectures using extensible processors, 18th International Conference on VLSI Design, p.551556, 2005.

Y. Jin, N. Satish, K. Ravindran, and K. Keutzer, An automated exploration framework for FPGA-based soft multiprocessor systems, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, 2005.
DOI : 10.1145/1084834.1084903

M. A. Roger, B. M. Peel, and . Cook, Occam on eld-programmable gate arrays -fast prototyping of parallel embedded systems, the Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000.

M. David and R. Taylor, Occam : An overview, Microprocessors and Microsystems, p.7379, 1984.

S. Muhammed-al-mulhem, R. Ali, O. Benmouhoub, and . Hammami, Formal semantics of visual occam Mocsoc : Multiprocessor on chip synthesis from occam, Computer Languages The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), p.99113, 1998.

C. Stephen and . Johnson, The lex yacc page Available on : http://dinosaur. compilertools.net

C. Ciordas, K. Goossens, A. Radulescu, and T. Basten, Noc monitoring : impact on the design ow, IEEE International Symposium on Circuits and Systems, 2006.

C. Ciordas, T. Basten, A. Radulescu, K. Goossens, and J. Van-meerbergen, An event-based monitoring service for networks on chip, ACM Trans. Des. Autom. Electron. Syst, vol.10, issue.4, p.702723, 2005.

C. Ciordas, A. Hansson, K. Goossens, and T. Basten, A monitoring-aware network-on-chip design ow, IEEE 9th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools, p.97106, 2006.

L. Tedesco, A. M. , D. Garibotti, N. Calazans, and F. Moraes, Trac generation and performance evaluation for mesh-based nocs, 18th ACM Symposium on Integrated Circuits and Systems Design, p.184189, 2005.

P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, Performance evaluation and design trade-os for network-on-chip interconnect architectures, IEEE Transactions on computers, pp.1025-1040, 2005.

A. Hegedus, G. M. Maggio, and L. Kocarev, A ns-2 simulator utilizing chaotic maps for network-on-chip trac analysis, IEEE International Symposium on Circuits and Systems, ISCAS, p.33753378, 2005.

M. El and S. , On-chip monitoring of single-and multiprocessor hardware real-time operating systems, Proceedings of the 8th International Conference on Real-Time Computing Systems and Applications (RTCSA), 2002.

N. Genko, D. Atienza, G. De-micheli, L. Benini, J. M. Mendias et al., A Novel Approach for Network on Chip Emulation, 2005 IEEE International Symposium on Circuits and Systems, p.23652368, 2005.
DOI : 10.1109/ISCAS.2005.1465100

K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. L. Sangiovanni-vincentelli, System-level design: orthogonalization of concerns and platform-based design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.12, 2000.
DOI : 10.1109/43.898830

R. Benmouhoub and O. Hammami, Mocdex : Multiprocessor on chip multiobjective design space exploration with direct execution, The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SA- SIMI), 2006.

. Xilinx and . Ug012, virtex-ii pro and virtex-ii pro x fpga user guide

. Xilinx, Xapp 290 (v1.2) : Two ows for partial reconguration : Module based or dierence based. 09/09 Available on, 2004.

C. A. Coello, D. V. Veldhuizen, and G. B. Lamont, Evolutionary Algorithms for Solving Multi-Objective Problems of Genetic Algorithms and Evolutionary Computation, Academic, vol.5, 2002.

D. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach, 1999.

A. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00012749

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors, Proceedings of the 18th IEEE International Conference on VLSI Design, pp.551-556, 2005.

Y. Jin, N. Satish, K. Ravindran, and K. Keutzer, An automated exploration framework for FPGA-based soft multiprocessor systems, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, pp.273-278, 2005.
DOI : 10.1145/1084834.1084903

N. K. Bambha and S. S. Bhattacharyya, Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors, IEEE Transactions on Parallel and Distributed Systems, vol.16, issue.2, pp.99-112, 2005.
DOI : 10.1109/TPDS.2005.20

. Xilinx, Embedded system tools guide

I. Aouadi, R. B. Mouhoub, and O. Hammami, System on a programmable chip oriented JPEG-2000 entropy coder implementation for multimedia embedded systems, 2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE., pp.447-448, 2005.
DOI : 10.1109/ICCE.2005.1429910

R. B. Mouhoub, I. Aouadi, and O. Hammami, System on programmable chip platform based design of JPEG-2000 entropy coder, Proceedings of the 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '04), pp.103-106, 2004.

C. A. Coello, An updated survey of GA-based multiobjective optimization techniques, ACM Computing Surveys, vol.32, issue.2, pp.109-143, 2000.
DOI : 10.1145/358923.358929

K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, A fast and elitist multiobjective genetic algorithm: NSGA-II, IEEE Transactions on Evolutionary Computation, vol.6, issue.2, pp.182-197, 2002.
DOI : 10.1109/4235.996017

M. T. Jensen, Reducing the Run-Time Complexity of Multiobjective EAs: The NSGA-II and Other Algorithms, IEEE Transactions on Evolutionary Computation, vol.7, issue.5, pp.503-515, 2003.
DOI : 10.1109/TEVC.2003.817234

K. Ghali and O. Hammami, Embedded processor characteristics specification through multiobjective evolutionary algorithms, 2003 IEEE International Symposium on Industrial Electronics ( Cat. No.03TH8692), pp.907-912, 2003.
DOI : 10.1109/ISIE.2003.1267942

K. Ghali and O. Hammami, Embedded processors optimization with hardware in the loop, 2004 IEEE International Symposium on Industrial Electronics, pp.561-564, 2004.
DOI : 10.1109/ISIE.2004.1571868

F. Fummi, S. Martini, G. Perbellini, and M. Poncino, Native ISS-SystemC integration for the co-simulation of multiprocessor SoC, Proceedings of the IEEE Conference and Exhibition on Design, Automation and Test in Europe, pp.564-569, 2004.

F. Ghenassia, Transaction-Level Modeling with SystemC TLM Concepts and Applications for Embedded Systems, 2005.

I. Aouadi, R. Benmouhoub, and O. Hammami, System on a programmable chip oriented JPEG-2000 entropy coder implementation for multimedia embedded systems, 2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE., pp.447-448, 2005.
DOI : 10.1109/ICCE.2005.1429910

N. K. Bambha and S. S. Bhattacharyya, Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors, IEEE Transactions on Parallel and Distributed Systems, pp.99-112, 2005.
DOI : 10.1109/TPDS.2005.20

R. Benmouhoub, I. Aouadi, and O. Hammami, System on programmable chip plateform based design of jpeg-2000 entropy coder, Workshop on synthesis and system integration of mixed information technologies (SASIMI'04), pp.103-106, 2004.

S. D. Brookes, C. A. Hoare, and A. W. Roscoe, A Theory of Communicating Sequential Processes, Journal of the ACM, vol.31, issue.3, pp.560-599, 1984.
DOI : 10.1145/828.833

D. E. Culler, A. Gupta, and J. P. Singh, Parallel Computer Architecture: A Hardware/Software Approach, 1997.

D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation , DAC '01, pp.518-523, 2001.
DOI : 10.1145/378239.379015

URL : https://hal.archives-ouvertes.fr/hal-00008074

F. Ghenassia, Transaction-Level Modeling with SystemC TLM Concepts and Applications for Embedded Systems, 2005.

C. Hoare, Communicating sequential processes, Communications of the ACM, vol.21, issue.8, pp.666-677, 19781978.
DOI : 10.1145/359576.359585

Y. Jin, N. Satish, K. Ravindran, and K. Keutzer, An automated exploration framework for FPGA-based soft multiprocessor systems, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, 2005.
DOI : 10.1145/1084834.1084903

M. Keating and P. Bricaud, Reuse Methodology Manual for System-On-A-Chip Designs, 14] MPI. Message passing interface. Available on, 2002.
DOI : 10.1007/978-1-4757-2887-3

P. H. Neil and C. Brown, An Introduction to the Kent C++ CSP Library, 2003.

K. R. Gupta and S. Pande, Compilation techniques for parallel systems, Parallel Computing, vol.25, issue.13-14, pp.1741-1783, 1999.
DOI : 10.1016/S0167-8191(99)00086-1

R. J. Anderson and L. Snyder, A comparison of shared and nonshared memory models of parallel computation, Proc. of the IEEE, 1991.
DOI : 10.1109/5.92042

D. Skillicorn and D. Talia, Models and languages for parallel computation, ACM Computing Surveys, vol.30, issue.2, 1998.
DOI : 10.1145/280277.280278

F. Sun, N. K. Jha, S. Ravi, and A. Raghunathan, Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors, 18th International Conference on VLSI Design21] SystemVerilog. Systemverilog. Available on, pp.551-556, 2005.

W. Hasselbring, Programming languages and systems for prototyping concurrent applications, ACM Computing Surveys, vol.32, issue.1, 2002.
DOI : 10.1145/349194.349199

. Xilinx, Embedded system tools guide Available on

. Xilinx, Microblaze soft core processor Available on: http://www.xilinx.com/. [25] Xilinx. Xilinx fast simplex link ip Available on: http://www.xilinx.com/. References [1] A.A.Jerraya and W.Wolf. Multiprocessor Systems-on- Chips, 2004.

L. Benini and G. Micheli, Networks on chips: a new SoC paradigm, Computer, pp.70-78, 2002.
DOI : 10.1109/2.976921

W. Dally and B. Towles, Route packets not wires: Onchip inttercnnection networks, Design Automation Conference, pp.684-689, 2001.

F. Moraes, N. Calazans, A. Mello, M. Leandro, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, pp.69-93, 2004.
DOI : 10.1016/j.vlsi.2004.03.003

S. Kumar, A network on chip architecture and design methodology, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, pp.117-124, 2002.
DOI : 10.1109/ISVLSI.2002.1016885

J. Nollet, V. Marescaux, T. Verkest, D. Vernalde, S. Lauwereins et al., Highly scalable network on chip for reconfigurable systems, IEEE International Symposium on System-on-Chip, pp.79-82, 2003.

F. Moraes, N. Calazans, A. Mello, L. Moller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, pp.69-93, 2004.
DOI : 10.1016/j.vlsi.2004.03.003

D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou et al., NoC synthesis flow for customized domain specific multiprocessor systems-on-chip, IEEE Transactions on Parallel and Distributed Systems, vol.16, issue.2, pp.113-129, 2005.
DOI : 10.1109/TPDS.2005.22

L. Tedesco, A. M. Garibotti, N. Calazans, and F. Moraes, Traffic generation and performance evaluationfor meshbased nocs, 18th ACM Symposium on Integrated Circuits and Systems Design, pp.184-189, 2005.

M. Ivanov, A. Saleh, R. P. Pande, C. Grecu, and . Jones, Performance evaluation and design trade-offs for networkon-chip interconnect architectures, IEEE Transactions on computers, pp.1025-1040, 2005.

G. M. Kocarev, L. Hegedus, and A. Maggio, A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis, IEEE International Symposium on Circuits and Systems, ISCAS, pp.3375-3378, 2005.

L. Noordergraaf and R. Zak, SMP System Interconnect Instrumentation for Performance Analysis, ACM/IEEE SC 2002 Conference (SC'02), pp.1-9, 2002.
DOI : 10.1109/SC.2002.10011

M. Martonosi, D. Ofelt, and M. Heinrich, Integrating performance monitoring and communication in parallel computers, SIGMETRICS '96: Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pp.138-147, 1996.

N. Genko, D. Atienza, G. De-micheli, L. Benini, J. M. Mendias et al., A Novel Approach for Network on Chip Emulation, 2005 IEEE International Symposium on Circuits and Systems, pp.2365-2368, 2005.
DOI : 10.1109/ISCAS.2005.1465100

C. Ciordas, T. Basten, A. Radulescu, K. Goossens, and J. V. Meerbergen, An event-based monitoring service for networks on chip, ACM Transactions on Design Automation of Electronic Systems, vol.10, issue.4, pp.702-723, 2005.
DOI : 10.1145/1109118.1109126

. Xilinx, Available on: http://www.xilinx.com

R. Benmouhoub, I. Aouadi, and O. Hammami, System on programmable chip plateform based design of jpeg-2000 entropy coder, Workshop on synthesis and system integration of mixed information technologies (SASIMI'04), pp.103-106, 2004.

I. Aouadi, R. Benmouhoub, and O. Hammami, System on a programmable chip oriented JPEG-2000 entropy coder implementation for multimedia embedded systems, 2005 Digest of Technical Papers. International Conference on Consumer Electronics, 2005. ICCE., 2005.
DOI : 10.1109/ICCE.2005.1429910

. Xilinx, Xilinx fast simplex link ip Available on

K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. L. Sangiovanni-vincentelli, System-level design: orthogonalization of concerns and platform-based design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.12, 2000.
DOI : 10.1109/43.898830

R. Benmouhoub and O. Hammami, Mocdex: Multiprocessor on chip multiobjective design space exploration with direct execution, The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.254-261, 2006.

R. Benmouhoub and O. Hammami, System-level design methodology with direct execution for multiprocessors on sopc, IEEE Seventh International Symposium on Quality Electronic Engineering Design, pp.781-786, 2006.

R. Benmouhoub, O. Hammami, R. Benmouhoub, and O. Hammami, Multiprocessor on chip : Beating the simulation wall through multiobjective design space exploration with direct execution Mocsoc: Multiprocessor on chip synthesis from occam, 5th IEEE International Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems (IPDPS) The 13 th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.246-253, 2006.

W. H. Ho and T. M. Pinkston, A design methodology for efficient application-specific on-chip interconnects, IEEE Transactions on Parallel and Distributed Systems, pp.174-190, 2006.
DOI : 10.1109/TPDS.2006.15