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Mixed-signal clock-skew calibration in time-interleaved analog-to-digital converters

Abstract : Clock-skew errors in time-interleaved ADCs importantly degrade the linearity of such converters. These nearly constant but unknown errors, that must not be confused with random jitter, prevent time-interleaved ADCs from performing uniform sampling. There are some different techniques of facing clock-skew errors : two-ranks sample-and-hold, channel randomization, global passive sampling, clock-edge reassignment, all-digital calibration techniques and all-analog calibration techniques. We propose a new kind of mixed-signal clock-skew calibration technique. Compared to the all-digital ones, ours distinguishes itself by the simplicity of its hardware elements. On the other hand, compared to the all-analog ones, ours keeps the inherent robustness of a digital clock-skew detection. A demonstrator shows the feasibility of our technique. This demonstrator consists of two 10-bit commercial ADCs, an FPGA to implement a digital clock-skew detector and an ASIC in a CMOS 0.35 µm technology to implement a digitally trimmable multi-phase sampling clock generator. In this highly hostile environment of interconnected discrete components, our demonstrator can correct an initial clock-skew of thousands of picoseconds with a granularity of 1.8 picoseconds.
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https://pastel.archives-ouvertes.fr/pastel-00002869
Contributor : Ecole Télécom Paristech <>
Submitted on : Friday, September 28, 2007 - 8:00:00 AM
Last modification on : Friday, July 31, 2020 - 10:44:05 AM
Long-term archiving on: : Saturday, November 26, 2016 - 3:07:44 PM

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  • HAL Id : pastel-00002869, version 1

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David Camarero de la Rosa. Mixed-signal clock-skew calibration in time-interleaved analog-to-digital converters. domain_other. Télécom ParisTech, 2007. English. ⟨pastel-00002869⟩

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