Surviving the SOC Revolution: A Guide to Platform-Based Design, 1999. ,
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable architecture, IIEEE International Conference on Acoustics Speech and Signal Processing, p.4194, 2002. ,
DOI : 10.1109/ICASSP.2002.1004944
P, 'FIGARO ? An Automatic Tool Flow for Designs with Dynamic Reconfiguration, Proceedings of the 13 th International Symposium on Field-Programmable Gate Arrsays, pp.262-266, 2005. ,
Hardware/software partitioning for multi-function systems, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, pp.516-521, 1997. ,
DOI : 10.1109/ICCAD.1997.643588
Algorithmic aspects of hardware/software partitioning, ACM Transactions on Design Automation of Electronic Systems, vol.10, issue.1, pp.136-156 ,
DOI : 10.1145/1044111.1044119
SystemC and the future of design languages: opportunities for users and research, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings., pp.69-78, 2003. ,
DOI : 10.1109/SBCCI.2003.1232807
Design For Verification of SystemC Transaction Level Models, Proceedings of the Design, Automation and Test in Europe Conference, DATE'05, 2005. ,
URL : https://hal.archives-ouvertes.fr/hal-00181571
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC, Proceedings of the Design, Automation and Test in Europe Conference, p.2, 2002. ,
A Higher Level System Communication Model for Object-Oriented Specification and Design of Embedded Systems, pp.69-78, 2001. ,
Transaction Level Modelling: An Overview, Proceedings of ACM international Conference on Hardware/Software codesign and system synthesis, pp.19-24, 2003. ,
Object-oriented modeling and synthesis of SystemC specifications, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), pp.238-243, 2004. ,
DOI : 10.1109/ASPDAC.2004.1337573
Framed complexity analysis in SystemC for multi-level design space exploration, Euromicro Symposium on Digital System Design, 2003. Proceedings., pp.416-423, 2003. ,
DOI : 10.1109/DSD.2003.1231975
High-level System Modelling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case study, Proceedings of the Design, automation and Test in Europe conference, pp.538-543, 2004. ,
A modular simulation framework for architectural exploration of on-chip interconnection networks, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis , CODES+ISSS '03, pp.7-12, 2003. ,
DOI : 10.1145/944646.944648
Behavioral synthesis with SystemC, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001. ,
DOI : 10.1109/DATE.2001.914995
Synthesis of embedded systemC design: a case study of digital neural networks, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.248-253, 2004. ,
DOI : 10.1109/DATE.2004.1269239
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems, Proceedings of the Design, automation and Test in Europe conference, pp.253-258, 2005. ,
URL : https://hal.archives-ouvertes.fr/hal-00181858
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform, Proceedings of the tenth international symposium on Hardware/software codesign , CODES '02, pp.151-156, 2002. ,
DOI : 10.1145/774789.774820
A power estimation methodology for systemC transaction level models, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, pp.142-147, 2005. ,
DOI : 10.1145/1084834.1084874
An area estimation methodology for FPGA based designs at systemc-level, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.129-132, 2004. ,
DOI : 10.1145/996566.996606
Parallel Modelling Paradigm in multimedia applications: Mapping and scheduling onto a Multi-processor system-on, Proceedings of the International Global Signal Processing Conference, 2004. ,
A design flow for partially reconfigurable hardware, ACM Transactions on Embedded Computing Systems, vol.3, issue.2, pp.257-283, 2004. ,
DOI : 10.1145/993396.993399
Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, pp.187-195, 2002. ,
DOI : 10.1145/503048.503076
Lx: a technology platform for customizable VLIW embedded processing, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), pp.203-213, 2000. ,
DOI : 10.1109/ISCA.2000.854391
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications, LNCS, pp.844-848, 2002. ,
DOI : 10.1007/3-540-45706-2_119
Hardware/software partitioning for multi-function systems, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, pp.516-521, 1997. ,
DOI : 10.1109/ICCAD.1997.643588
Magellan: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs, Proceedings of ACM international Conference on Hardware/Software Codesign and System Synthesis, pp.42-47, 2001. ,
Hardware/software partitioning of embedded systems with multiple hardware processes, IEE Proceedings on Computers and digital techniques, pp.285-294, 1997. ,
DOI : 10.1049/ip-cdt:19971367
Conservative Scheduling: using predicted variance to improve scheduling decisions in dynamic environments, Proceedings of ACM/IEEE Conference on Supercomputing, pp.31-46, 2003. ,
Hardware-software partitioning and pipelined scheduling of transformative applications, IEEE Transactions on Very Large Scale Integration systems, pp.193-208, 2002. ,
Configuration-sensitive process scheduling for FPGAbased computing platforms, Proceedings of the Design, automation and test in Europe, pp.16-20, 2004. ,
A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration, Proceedings Asia and South Pacific Design Automation Conference, pp.323-328, 2000. ,
Dynamic voltage scheduling using adaptive filtering of workload traces, VLSI Design 2001. Fourteenth International Conference on VLSI Design, pp.221-226, 2001. ,
DOI : 10.1109/ICVD.2001.902664
System-level synthesis using re-programmable components, [1992] Proceedings The European Conference on Design Automation, pp.2-7, 1992. ,
DOI : 10.1109/EDAC.1992.205881
Applying fuzzy logic to codesign partitioning, Proceedings IEEE Micro, pp.62-70, 1997. ,
DOI : 10.1109/40.591657
SOC architecture synthesis based on high-level IPs, IEICE Transaction fundamentals, vol.85, issue.12, 2004. ,
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures, Proceedings of the tenth international symposium on Hardware/software codesign , CODES '02, pp.205-210, 2002. ,
DOI : 10.1145/774789.774831
A HW/SW partitioning algorithm for dynamically reconfigurable architectures, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.729-734, 2001. ,
DOI : 10.1109/DATE.2001.915109
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model, Proceedings of the tenth international symposium on Hardware/software codesign , CODES '02, pp.199-204, 2002. ,
DOI : 10.1145/774789.774830
CRUSADE, Proceedings of the conference on Design, automation and test in Europe , DATE '99, pp.97-104, 1999. ,
DOI : 10.1145/307418.307461
Platform-independent methodology for partial reconfiguration, Proceedings of the first conference on computing frontiers on Computing frontiers , CF'04, pp.398-403, 2004. ,
DOI : 10.1145/977091.977148
The first real operating system for reconfigurable computers, Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001, pp.29-30, 2001. ,
DOI : 10.1109/ACAC.2001.903375
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems, Design, Automation and Test in Europe, pp.266-271, 2005. ,
DOI : 10.1109/DATE.2005.61
URL : https://hal.archives-ouvertes.fr/hal-00181860
A Framework to Support Run-Time Assured Dynamic Reconfiguration for Pervasive Computing Environments, 2006 1st International Symposium on Wireless Pervasive Computing, 2006. ,
DOI : 10.1109/ISWPC.2006.1613631
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), p.251, 2006. ,
DOI : 10.1109/ISVLSI.2006.38
URL : https://hal.archives-ouvertes.fr/lirmm-00102766
Ultra-low-power domain-specific multimedia processors, VLSI Signal Processing, IX, pp.461-470, 1996. ,
DOI : 10.1109/VLSISP.1996.558379
Targeting tiled architectures in design exploration, Proceedings International Parallel and Distributed Processing Symposium, p.8, 2003. ,
DOI : 10.1109/IPDPS.2003.1213317
A Dynamically Reconfigurable Architecture dealing with next Generation Telecommunications Constraints, Reconfigurable Architecture Workshop, 2002. ,
A reconfiguration Manager for Dynamically Reconfigurable Hardware, Transactions on IEEE Design & Test Computers, pp.452-460, 2005. ,
Power- Efficient Adaptive Viterbi Decoder, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.484-488, 2005. ,
Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA, 2004 International Conference on Image Processing, 2004. ICIP '04., pp.2841-2844, 2004. ,
DOI : 10.1109/ICIP.2004.1421696
Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375) ,
DOI : 10.1109/FPGA.1999.803674
Power-performance trade-offs for reconfigurable computing, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.116-121, 2004. ,
DOI : 10.1145/1016720.1016751
Techniques and mechanisms for dynamic reconfiguration in an image processor, Proceedings. 15th Symposium on Integrated Circuits and Systems Design, p.pp, 2002. ,
DOI : 10.1109/SBCCI.2002.1137655
Custom Memory Management Methodology: Exploration of Memory organisation for Embedded Multimedia System Design, 1998. ,
DOI : 10.1007/978-1-4757-2849-1
Memory size computation for multimedia processing applications, Proceedings of the 2006 conference on Asia South Pacific design automation , ASP-DAC '06, pp.802-807, 2006. ,
DOI : 10.1145/1118299.1118483
Workload prediction and dynamic voltage scaling for mpeg decoding, Asia and South Pacific Conference on Design Automation, 2006., pp.911-916, 2006. ,
DOI : 10.1109/ASPDAC.2006.1594802
MPEG-7 multimedia description schemes, IEEE Transactions on Circuits and Systems for Video Technology, vol.11, issue.6, pp.748-759, 2001. ,
DOI : 10.1109/76.927435
Dynamic voltage scheduling with buffers in low-power multimedia applications, ACM Transactions on Embedded Computing Systems, vol.3, issue.4, pp.686-705, 2004. ,
DOI : 10.1145/1027794.1027796
Frame-based dynamic voltage and frequency scaling for a MPEG decoder, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design , ICCAD '02, pp.732-737, 2002. ,
DOI : 10.1145/774572.774680
Trends in Wide area IP traffic patterns, a view from Ames internet exchange', ITC specialist seminar on IP Traffic Modeling, 2000. ,
Caching schemes for distributed video services, 1999 IEEE International Conference on Communications (Cat. No. 99CH36311), pp.994-999, 1999. ,
DOI : 10.1109/ICC.1999.765423
High-performance prefetching protocols for VBR prerecorded video, IEEE Network, vol.12, issue.6, pp.46-55, 1998. ,
DOI : 10.1109/65.752644
Adaptive workload-dependent scheduling for large-scale content delivery systems, IEEE Transactions on Circuits and Systems for Video Technology, vol.11, issue.3, pp.426-439, 2001. ,
DOI : 10.1109/76.911166
Neighbor Cache Prefetching for Multimedia Image and Video Processing, IEEE Transactions on Multimedia, vol.6, issue.4, pp.539-552, 2004. ,
DOI : 10.1109/TMM.2004.830806
Capturing dynamic memory reference behaviour with adaptive cache topology, Proceedings International Conference on Architectural support for programming language and operating systems, pp.240-250, 1998. ,
Towards effective embedded processors in codesigns, Proceedings of the ninth international symposium on Hardware/software codesign , CODES '01, pp.79-84, 2001. ,
DOI : 10.1145/371636.371687
An adaptive cache coherence protocol specification for parallel input/output systems, IEEE Transactions on Parallel and Distributed Systems, vol.15, issue.6, pp.533-545, 2004. ,
DOI : 10.1109/TPDS.2004.1
Run time adaptive cache hierarchy management via reference analysis, Proceedings of International Symposium on Computer Architecture, pp.315-326, 1997. ,
Reconfigurable caches and their application to media processing, Proceedings International Symposium on Computer Architecture, pp.214-224, 2000. ,
Performance and memory-access characterization of data mining applications, Workload Characterization: Methodology and Case Studies. Based on the First Workshop on Workload Characterization, p.49, 1998. ,
DOI : 10.1109/WWC.1998.809358
Phase tracking and prediction, Proceedings International Symposium on Computer Architecture, pp.336-347, 2003. ,
Managing multi-configuration hardware via dynamic working set analysis, Proceedings International Symposium on Computer Architecture, pp.233-244, 2002. ,
An architectural framework for runtime optimization, IEEE Transactions on Computers, vol.50, issue.6, pp.567-589, 2001. ,
DOI : 10.1109/12.931894
Platform-independent dynamic reconfiguration of distributed applications, Proceedings International Workshop on Future Trends of Distributed Computing Systems, pp.286-291, 2004. ,
Speculative techniques for high level synthesis of control intensive designs, Proceedings Design Automation Conference, pp.269-272, 2001. ,
Optimal Period of Workload Redistribution for Dynamic Bulk Synchronous Computations in Heterogeneous Computing Systems, Proceedings International Parallel and distributed Processing Symposium, p.242, 2004. ,
DOI : 10.1007/s11227-006-4666-9
Transition Phase Classification and Prediction, 11th International Symposium on High-Performance Computer Architecture, pp.278-289, 2005. ,
DOI : 10.1109/HPCA.2005.39
M, 'detecting recurrent phase behaviour under real-system variability, Proceedings IEEE International Workload Characterization Conference, pp.13-23, 2005. ,
Data locality analysis of the SPEC95', Workshop on Digest of Performance Analysis and its Impact on Design, pp.78-84, 1998. ,
Constructing a Non-Linear Model with Neural Networks for Workload Characterization, 2006 IEEE International Symposium on Workload Characterization, pp.150-159, 2006. ,
DOI : 10.1109/IISWC.2006.302739
Empirical modeling of very large data sets using neural networks, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium, pp.302-307, 2000. ,
DOI : 10.1109/IJCNN.2000.859413
SPEClite: using representative samples to reduce SPEC CPU2000 workload, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538), pp.15-23, 2001. ,
DOI : 10.1109/WWC.2001.990740
Enhancing prototype Reduction schemes with recursion: A Method Applicable for Large Data Sets, IEEE Transactions on Systems, Man and cybernetics, vol.34, issue.3, pp.1384-1397, 2004. ,
Analyzing Software Measurement Data with Clustring Techniques, IEEE Transactions on Intelligent Systems, pp.20-27, 2004. ,
An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), p.5, 2006. ,
DOI : 10.1109/ISVLSI.2006.20
On the Design of a Self-Reconfigurable SoPC Based Cryptographic Engine, Proceedings International Conference on Distributed Computing Systems Workshops, pp.876-881, 2004. ,
Scheme of SoPC-Based Reconfigurable Controllers, Proceedings Euromicro Conference on Digital System Design, pp.364-371, 2005. ,
Parametric yield in FPGAs due to within-die delay variations, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays , FPGA '07, pp.178-187, 2007. ,
DOI : 10.1145/1216919.1216949
Fast Configuration of an Energy-Efficient Branch Predictor, Proceedings Emerging VLSI Technologies and Architectures, p.289, 2006. ,
System-level modeling of dynamically reconfigurable hardware with SystemC, Proceedings International Parallel and Distributed Processing Symposium, p.8, 2003. ,
DOI : 10.1109/IPDPS.2003.1213321
SystemC-based Design Methodology for Reconfigurable System on Chip, Proceedings of the Euromicro Conference on Digital System Design, pp.364-371, 2005. ,
SUIF, ACM SIGPLAN Notices, vol.29, issue.12, pp.31-37, 1994. ,
DOI : 10.1145/193209.193217
JPEG2000: Image Compression Fundamentals, Standards and Practice, Journal of Electronic Imaging, vol.11, issue.2, 2001. ,
DOI : 10.1117/1.1469618
Neural networks, financial trading and the efficient markets hypothesis', Conferences in research and practice in information technology series, pp.241-249, 2002. ,
QoS Provisioning Dynamic Connection-Admission Control for Multimedia Wireless Networks Using a Hopfield Neural Network, IEEE Transactions on Vehicular Technology, vol.53, issue.1, pp.106-117, 2004. ,
DOI : 10.1109/TVT.2003.822000
Recurrent neural networks and robust time series prediction, IEEE Transactions on Neural Networks, vol.5, issue.2, pp.240-254, 1994. ,
DOI : 10.1109/72.279188
Multi-step-ahead prediction using dynamic recurrent neural networks, Neural Networks, vol.13, issue.7, pp.765-786, 2000. ,
DOI : 10.1016/S0893-6080(00)00048-4
Approximation of dynamical Time-variant systems by continuous-time recurrent neural networks, IEEE Transactions on Circuits and Systems II: Express Briefs, pp.656-660, 2005. ,
Approximation by superpositions of a sigmoidal function, Mathematics of Control, Signals, and Systems, vol.27, issue.4, pp.303-314, 1989. ,
DOI : 10.1007/BF02551274
Learning internal representations by error propagation', Parallel Distributed Processing Explorations in the Microstructure of Cognition, pp.318-362, 1986. ,
NARX models of an industrial power plant gas turbine, IEEE Transactions on Control Systems Technology, vol.13, issue.4, pp.599-604, 2005. ,
DOI : 10.1109/TCST.2004.843129
Computational capabilities of recurrent NARX neural networks', IEEE Transactions on Systems, Man and Cybernetics, vol.27, issue.2, pp.208-215, 1997. ,
Delay Damage Model Selection Algorithm for NARX Neural Networks, IEEE Transactions on Signal Processing, vol.45, issue.11, pp.2719-2730, 1997. ,
Computational capabilities of recurrent NARX neural networks, IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), vol.27, issue.2, pp.208-223, 1997. ,
DOI : 10.1109/3477.558801
An experimental comparison of recurrent neural network', Proceedings In Advances in Neural Information Systems Processings, pp.697-704, 1995. ,
The organization of the behavior', 1949. ,
QoS Provisioning Dynamic Connection-Admission Control for Multimedia Wireless Networks Using a Hopfield Neural Network, IEEE Transactions on Vehicular Technology, vol.53, issue.1, pp.106-117, 2004. ,
DOI : 10.1109/TVT.2003.822000
Time series forecasting using flexible neural tree model', Information sciences 174, pp.219-235, 2005. ,
Incremental training of first order recurrent neural networks to predict a context-sensitive language, Neural Networks, vol.16, issue.7, pp.955-972, 2003. ,
DOI : 10.1016/S0893-6080(03)00054-6
Combining Artificial Neural Networks and Statistics for Stockmarket Forecasting, ACM Annual Computer Science Conference, pp.257-264, 1993. ,
A simple SVM Algorithm, Proceedings International Joint Conference on Neural Networks, IJCNN '02, pp.2393-2398, 2002. ,
Nearest prototype classifier designs: An experimental study, International Journal of Intelligent Systems, vol.8, issue.12, pp.1445-1473, 2001. ,
DOI : 10.1002/int.1068
Self-Organizing Maps and Learning Vector Quantization for Feature Sequences, Neural Processing Letters, pp.151-159, 1999. ,
A comparative study of neural network and Box-Jenkins ARIMA modeling in time series prediction, Proceedings of the 26 th International Conference on Computers and Industrial Engineering, pp.371-375, 2002. ,
DOI : 10.1016/S0360-8352(02)00036-0
System-Level modeling of dynamically reconfigurable co-processors, Proceedings of the International Conference on FPL, pp.881-885, 2004. ,
A framework for reconfigurable computing: task scheduling and context management, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, issue.6, pp.858-873, 2001. ,
DOI : 10.1109/92.974899
Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks, IEEE Transactions on Computers, vol.53, issue.11, pp.1393-1407, 2004. ,
DOI : 10.1109/TC.2004.99
Processors: A New Era in chip design, IEEE Transactions on Computer, vol.38, issue.7, pp.51-59, 2005. ,
System Exploration of SystemC Designs, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), p.335, 2006. ,
DOI : 10.1109/ISVLSI.2006.87
Neural Network Based Memory Access Prediction Support for SoC Dynamic Reconfiguration, Proceedings of the WCCI 2006 IEEE International Joint Conference in Neural Network ,
Neural Network Based Variable Workload Prediction Driven System Level Design ,
Optimisation multiobjectif, Edition Eyrolles ,
Space Exploration of Behavioral Synthesis Options on Area and Performance, Third IEEE International Conference on Systems, Signals & Devices SSD'05 ,
Space Exploration of Behavioral Synthesis Options on Area, Performance and Power consumptionDesign Space Exploration of SystemC SOM Implementation, IEEE International Conference on Microelectronics, ICM'05 3rd IEEE International Conference on Information & communications technology ICICT'05, 2005. ,
JPEG2000: Image Compression Fundamentals, Standards and Practice, Journal of Electronic Imaging, vol.11, issue.2, 2001. ,
DOI : 10.1117/1.1469618
Time-series forecasting using flexible neural tree model, Information Sciences, vol.174, issue.3-4, pp.219-235, 2005. ,
DOI : 10.1016/j.ins.2004.10.005
Incremental training of first order recurrent neural networks to predict a context-sensitive language, Neural Networks, vol.16, issue.7, pp.955-972, 2003. ,
DOI : 10.1016/S0893-6080(03)00054-6
A Constructive Algorithm For Feedforward Neural Networks With Incremental Training on circuits and systems-I: fundamental theory and applications, IEEE Transactions, vol.49, issue.12, 2002. ,
Time Series Prediction with Ensemble Models, International Joint Conference on Neural Network, 2004. ,
Performance Evaluation of Neural Network Prediction for Data Prefetching in Embedded Applications, Proceedings of the International Conference on Computer Science ICCS'06 Vienna, 2006. ,
A hybrid approach for training recurrent neural networks: application to multi-step-ahead prediction of noisy and large data sets, Accepté pour parution dans le journal Neural Computing & Applications ,
DOI : 10.1007/s00521-007-0116-8
SystemC Modeling of JPEG-2000 components : Discrete Wavelet Transform and Entropy coder, 3rd International Symposium on Image/Video communications over fixed and mobile networks, pp.13-15 ,
JPEG-2000 Workload Prediction for Adaptive System on Chip Entropy Coders Architecture, WCCI 2006 IEEE International Joint Conference in Neural Network ,