I. First and .. , 91 5.3.1 History capacitor switches, p.94

D. Second, 100 5.5.1 Unit cell, p.101

&. Blocker, G. Adjacent-levels-in, and .. , 84 5.1 SAW filter transfer function in GSM mode, p.88

L. Ideal-modelling-of-the, 90 5.5 Schematic of the first IIR stage (I path), 91 5.6 Schematic of the history capacitor switch . . . . . . . . . . . . . 92

. Buffering-of-the and P. Iir, 94 5.10 Schematic of the SINC 2 unit cell 95 5.11 Schematic of the SINC 2 reconfigurable unit cell 96 5.12 Example of a SINC 2 coefficient cell (coef 14) 97 5.14 Arrangement of SINC 2 coefficients into bank 99 5.15 Top view of the anti-alias filter 104 5.21 Design concept for clock phases generation Reconfiguration of the token ring using pass gates Buffering of the input clock signal, 106 5.24 Timing diagram of the entire clock phases in GSM mode . . . . . 108 5.25 Architecture of the 110 5.27 Unit capacitor layout . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.28 History capacitor layout . . . . . . . . . . . . . . . . . . . . . . . 111 5.29 Gradient cancellation within AAF coefficients . . . . . . . . . . . 113 5.30 Gradient cancellation at AAF top level, p.114

S. Evaluation, 117 6.3 Gain versus RF input frequency (GSM mode), p.119

=. Cpar and +. Cpar_ih, Cdec*0.015)/2 + 33e-15; printf('Parasitic capacitance: Cpar = %.2e\n',Cpar)

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