E. Mollick, Establishing Moore's Law, IEEE Annals of the History of Computing, vol.28, issue.3, 2006.
DOI : 10.1109/MAHC.2006.45

D. Franco, J. Naviner, and L. Naviner, Yield and reliability issues in nanoelectronic technologies, Annales des télécommunications, vol.61, issue.11 12, p.14221457, 2006.

P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, Modeling the eect of technology trends on the soft error rate of combinational logic, DSN '02: Proceedings of the 2002 International Conference on Dependable Systems and Networks, p.389398, 2002.

N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia et al., Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices, 2006 IEEE International Reliability Physics Symposium Proceedings, p.217225, 2006.
DOI : 10.1109/RELPHY.2006.251220

B. Laszlo and . Kish, End of moore's law: Thermal (noise) death of integration in micro and nano electronics, Physics Letters A, vol.305, pp.3-4144149, 2002.

M. Nicolaidis, Carry checking/parity prediction adders and alus. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.11, issue.1, p.121128, 2003.
DOI : 10.1109/tvlsi.2002.800526

URL : https://hal.archives-ouvertes.fr/hal-00013737

M. Nicolaidis and R. O. Duarte, Fault-secure parity prediction booth multipliers, IEEE Design and Test of Computers, vol.16, issue.3, p.90101, 1999.
DOI : 10.1109/54.785842

URL : https://hal.archives-ouvertes.fr/hal-00013808

D. Marienfeld, E. S. Sogomonyan, V. Ocheretnij, and M. Gossel, New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors, 14th Asian Test Symposium (ATS'05), p.7681, 2005.
DOI : 10.1109/ATS.2005.80

S. Mitra and E. J. Mccluskey, Which concurrent error detection scheme to choose ? Test Conference, Proceedings. International, p.985994, 2000.

K. Parag and . Lala, Self-checking and fault-tolerant digital design, 2001.

K. Mohanram and N. A. Touba, Cost-eective approach for reducing soft error failure rate in logic circuits, Proceedings. ITC 2003. International, 2003.

Q. Zhou and K. Mohanram, Gate sizing to radiation harden combinational logic. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.25, issue.1, p.155166, 2006.

A. K. Nieuwland, S. Jasarevic, and G. Jerin, Combinational logic soft error analysis and protection. On-Line Testing Symposium, pp.10-12, 2006.
DOI : 10.1109/iolts.2006.17

B. D. Sierawski, B. L. Bhuva, and L. W. Massengill, Reducing Soft Error Rate in Logic Circuits Through Approximate Logic Functions, IEEE Transactions on Nuclear Science, vol.53, issue.6, p.34173421, 2006.
DOI : 10.1109/TNS.2006.884352

A. Birolini, Quality and Reliability of Technical Systems: Theory-Practice- Management, 1994.

N. Ketan, I. L. Patel, J. P. Markov, and . Hayes, Evaluating circuit reliability under probabilistic gate-level fault models, Proceeding of the Twelfth International Workshop on Logic and Synthesis, p.5964, 2003.

S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices, Design, Automation and Test in Europe, p.282287, 2005.
DOI : 10.1109/DATE.2005.47

URL : https://hal.archives-ouvertes.fr/hal-00181530

S. Krishnaswamy, I. L. Markov, and J. P. Hayes, Logic Circuits Testing for Transient Faults, European Test Symposium (ETS'05), p.102107, 2005.
DOI : 10.1109/ETS.2005.27

D. T. Maí-correia-vasconcelos, L. Franco, J. Naviner, and . Naviner, Reliability analysis of combinational circuits based on a probabilistic binomial model, IEEE Northeast Workshop on Circuits and Systems, p.310313, 2008.

D. Franco, M. Correia, L. Naviner, and J. Naviner, Reliability of logic circuits under multiple simultaneous faults, 2008 51st Midwest Symposium on Circuits and Systems, 2008.
DOI : 10.1109/MWSCAS.2008.4616787

D. Franco, M. Correia, L. Naviner, and J. Naviner, Signal probability for reliability evaluation of logic circuits, Microelectronics Reliability, vol.48, issue.8-9, 2008.
DOI : 10.1016/j.microrel.2008.07.002

K. P. Parker and E. J. Mccluskey, Analysis of logic circuits with faults using input signal probabilities. Computers, IEEE Transactions, issue.5, p.24573578, 1975.

S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, Estimate of signal probability in combinational logic networks, [1989] Proceedings of the 1st European Test Conference, pp.132138-132150, 1989.
DOI : 10.1109/ETC.1989.36234

N. Ministère-délégué-À-la-recherche and . Technologies, A la découverte du nanomonde, 2003.

J. Gea-banacloche and L. B. Kish, Future Directions in Electronic Computing and Information Processing, Proceedings of the IEEE, vol.93, issue.10, p.18581863, 2005.
DOI : 10.1109/JPROC.2005.853549

M. R. Stan, P. D. Franzon, S. C. Goldstein, J. C. Lach, and M. M. Ziegler, Molecular electronics: from devices and interconnect to circuits and architecture, Proceedings of the IEEE, vol.9, issue.11, p.9119401957, 2003.
DOI : 10.1109/JPROC.2003.818327

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.220.1981

M. A. Breuer, S. K. Gupta, and T. M. Mak, Defect and error tolerance in the presence of massive numbers of defects, IEEE Design and Test of Computers, vol.21, issue.3, p.216227, 2004.
DOI : 10.1109/MDT.2004.8

L. Anghel, Les Limites technologiques du Silicium et Tolerance aux Fautes Laboratoire Techniques de l'Informatique et de la Microélectronique pour l, 2000.

R. Baumann, The impact of technology scaling on soft error rate performance and limits to the ecacy of error correction. Electron Devices Meeting, IEDM '02. Digest. International, p.329332, 2002.

T. Skotnicki, J. A. Hutchby, T. King, H. P. Wong, and F. Boeuf, The end of CMOS scaling, IEEE Circuits and Devices Magazine, vol.21, issue.1, p.1626, 2005.
DOI : 10.1109/MCD.2005.1388765

G. Bouriano, The future of nanocomputing, Computer, issue.8, p.364453, 2003.

D. Edenfeld, A. B. Kahng, M. Rodgers, and Y. Zorian, technology roadmap for semiconductors, Computer, vol.37, issue.1, p.4756, 2003.

A. Avizienis, J. Laprie, and B. Randell, Fundamental concepts of dependability, 2001.

X. Li, Deep Submicron CMOS VLSI Circuit Reliability Modeling, Simulation and Design, 2005.

N. Sirisantana, B. C. Paul, and K. Roy, Enhancing yield at the end of the technology roadmap, IEEE Design and Test of Computers, vol.21, issue.6, p.563571, 2004.
DOI : 10.1109/MDT.2004.86

Y. Zorian, D. Gizopoulos, C. Vandenberg, and P. Magarshack, Guest editors' introduction: Design for yield and reliability. Design & Test of Computers, IEEE, vol.21, issue.3, p.177182, 2004.

M. Sydow, Compare logic-array to asic-chip cost per good die. Chip Design Magazine

M. Levitt, The role of design in enhancing nanometer process yield. International Engineering Consortium Newsletter, 2006.

M. Miller, Manufacturing-aware design helps boost ic yield. EE Times website

H. Jack, Design for manufacturability (dfm)

Y. Zorian, Nanoscale design & test challenges, Computer, vol.38, issue.2, p.3639, 2005.
DOI : 10.1109/mc.2005.67

C. Constantinescu, Trends and challenges in vlsi circuit reliability. Micro, IEEE, vol.23, issue.4, p.1419, 2003.

R. Baumann, Soft Errors in Advanced Computer Systems, IEEE Design and Test of Computers, vol.22, issue.3, p.258266, 2005.
DOI : 10.1109/MDT.2005.69

P. Hazucha and C. Svensson, Impact of CMOS technology scaling on the atmospheric neutron soft error rate, IEEE Transactions on Nuclear Science, vol.47, issue.6, p.25862594, 2000.
DOI : 10.1109/23.903813

C. A. Lang-lisbôa, L. Carro, and E. Cota, Robops -arithmetic operators for future technologies, Informal Proceedings of 10th IEEE European Test Symposium, 2005.

M. Spica and T. M. Mak, Do we need anything more than single bit error correction (ECC)?, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.
DOI : 10.1109/MTDT.2004.1327993

M. Nicolaidis, Design for soft error mitigation. Device and Materials Reliability, IEEE Transactions on, vol.5, issue.3, p.405418, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00107331

C. He, M. F. Jacome, and G. De-veciana, A reconguration-based defecttolerant design paradigm for nanotechnologies, Design & Test of Computers IEEE, vol.22, issue.4, p.316326, 2005.

K. Nikolic, A. Sadek, and M. Forshaw, Architectures for reliable computing with unreliable nanodevices, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516), p.254259, 2001.
DOI : 10.1109/NANO.2001.966429

P. K. Lala and A. Walker, On-line error detectable carry-free adder design. Defect and Fault Tolerance in VLSI Systems, Proceedings. 2001 IEEE International Symposium on, p.6671, 2001.

B. Parhami, Approach to the design of parity-checked arithmetic circuits. Signals, Systems and Computers, Conference Record of the Thirty-Sixth Asilomar Conference on, 2002.

G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, and A. Salsano, A signed digit adder with error correction and graceful degradation capabilities. On-Line Testing Symposium, Proceedings. 10th IEEE International, pp.141-146, 2004.

J. Han and P. Jonker, A system architecture solution for unreliable nanoelectronic devices, Nanotechnology IEEE Transactions on, vol.1, issue.4, p.201208, 2002.

F. G. De-lima-kastensmidt, G. Neuberger, R. F. Hentschke, L. Carro, and R. Reis, Designing fault-tolerant techniques for SRAM-based FPGAs, IEEE Design and Test of Computers, vol.21, issue.6, p.552562, 2004.
DOI : 10.1109/MDT.2004.85

S. Almukhaizim and Y. Makris, Fault tolerant design of combinational and sequential logic based on a parity check code. Defect and Fault Tolerance in VLSI Systems, Proceedings. 18th IEEE International Symposium on, p.563570, 2003.

C. A. Lisbôa and L. Carro, Arithmetic operators robust to multiple simultaneous upsets. Defect and Fault Tolerance in VLSI Systems, DFT 2004. Proceedings. 19th IEEE International Symposium on, p.289297, 2004.

E. Schüler and L. Carro, Increasing fault tolerance to multiple upsets using digital sigma-delta modulators. On-Line Testing Symposium, IOLTS 2005. 11th IEEE International, p.255259, 2005.

C. A. Lisbôa, E. Schüler, and L. Carro, Going beyond tmr for protection against multiple faults. Integrated Circuits and Systems Design, 18th Symposium on, p.8085, 2005.

A. Schmid and Y. Leblebici, Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.12, issue.11, p.11561166, 2004.

F. Peper, J. Lee, F. Abo, T. Isokawa, S. Adachi et al., Faulttolerance in nanocomputers: a cellular array approach, Nanotechnology IEEE Transactions on, vol.3, issue.1, p.187201, 2004.

C. Lazzari, L. Anghel, and R. A. Reis, On implementing a soft error hardening technique by using an automatic layout generator: case study. On-Line Testing Symposium, IOLTS 2005. 11th IEEE International, p.2934, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00015449

N. Ketan, I. L. Patel, and . Markov, Error-correction and crosstalk avoidance in dsm busses, IEEE Trans. Very Large Scale Integr. Syst, vol.12, issue.10, p.10761080, 2004.

P. Chan, G. A. Jullien, L. Imbert, V. S. Dimitrov, and G. H. Mcgibney, Fault-tolerant computation within complex r lters, Signal Processing Systems, p.316320, 2004.
DOI : 10.1109/sips.2004.1363069

D. Marculescu, Energy Bounds for Fault-Tolerant Nanoscale Designs, Design, Automation and Test in Europe, p.7479, 2005.
DOI : 10.1109/DATE.2005.135

URL : https://hal.archives-ouvertes.fr/hal-00181498

Y. S. Dhillon, A. U. Diril, A. Chatterjee, and A. D. Singh, Analysis and optimization of nanometer cmos circuits for soft-error tolerance. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.14, issue.5, p.514524, 2006.

S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, and Y. Xie, Reliability-Centric High-Level Synthesis, Design, Automation and Test in Europe, p.12581263, 2005.
DOI : 10.1109/DATE.2005.258

URL : https://hal.archives-ouvertes.fr/hal-00181301

M. Sachdev and J. Pineda-de-gyvez, Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits, 2007.
DOI : 10.1007/0-387-46547-2

R. C. Ogus, The probability of a correct output from a combinational circuit. Computers, IEEE Transactions, issue.5, p.24534544, 1975.

S. P. Dokouzgiannis and J. M. Kontoleon, Exact reliability analysis of combinational logic circuits, IEEE Transactions on Reliability, vol.37, issue.5, p.493500, 1988.
DOI : 10.1109/24.9870

A. Bogliolo, M. Damiani, P. Olivo, and B. Ricco, Reliability evaluation of combinational logic circuits by symbolic simulation, Proceedings 13th IEEE VLSI Test Symposium, p.235242, 1995.
DOI : 10.1109/VTEST.1995.512643

M. Omana, D. Rossi, and C. Metra, Model for transient fault susceptibility of combinational circuits: On-line testing (guest editors: Cecilia metra and matteo sonza reorda), Journal of Electronic Testing, vol.20, issue.9, p.501509, 2004.

B. Zhang, W. Wang, and M. Orshansky, Faser: fast analysis of soft error susceptibility for cell-based designs. Quality Electronic Design, ISQED '06. 7th International Symposium on, 2006.

N. Miskov-zivanov and D. Marculescu, Circuit reliability analysis using symbolic techniques. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.25, issue.12, p.26382649, 2006.

R. R. Rao, K. Chopra, D. T. Blaauw, and D. M. Sylvester, Computing the soft error rate of a combinational logic circuit using parameterized descriptors . Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.26, issue.3, p.468479, 2007.

S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, Probabilistic transfer matrices in symbolic reliability analysis of logic circuits, ACM Transactions on Design Automation of Electronic Systems, vol.13, issue.1, p.135, 2008.
DOI : 10.1145/1297666.1297674

T. Rejimon and S. Bhanja, An accurate probabilistic model for error detection. VLSI Design, 18th International Conference on, p.717722, 2005.

T. Rejimon and S. Bhanja, Scalable probabilistic computing models using bayesian networks. Circuits and Systems, 48th Midwest Symposium on, p.712715, 2005.
DOI : 10.1109/mwscas.2005.1594200

T. Rejimon and S. Bhanja, Time and space ecient method for accurate computation of error detection probabilities in vlsi circuits. Computers and Digital Techniques, IEE Proceedings, vol.152, issue.5, p.679685, 2005.

J. Han, E. Taylor, J. Gao, and J. Fortes, Faults, error bounds and reliability of nanoelectronic circuits. Application-Specic Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on, p.247253, 2005.

G. Asadi and M. B. Tahoori, An Analytical Approach for Soft Error Rate Estimation in Digital Circuits, 2005 IEEE International Symposium on Circuits and Systems, p.29912994, 2005.
DOI : 10.1109/ISCAS.2005.1465256

D. Bhaduri, S. Shukla, P. Graham, and M. Gokhale, Scalable techniques and tools for reliability analysis of large circuits. VLSI Design, Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on, p.705710, 2007.

R. Mihir, K. Choudhury, and . Mohanram, Accurate and scalable reliability analysis of logic circuits, DATE '07: Proceedings of the conference on Design, automation and test in Europe, p.14541459, 2007.

M. P. Baze and S. P. Buchner, Attenuation of single event induced pulses in CMOS combinational logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, p.22172223, 1997.
DOI : 10.1109/23.659038

V. L. Levin, Probability analysis of combination systems and their reliability, Engin. Cybernetics, issue.6, p.7884, 1964.

B. Krishnamurthy and I. G. Tollis, Improved techniques for estimating signal probabilities . Computers, IEEE Transactions on, vol.38, issue.7, p.10411045, 1989.

M. A. Kharji and S. A. , A new heuristic algorithm for estimating signal and detection probabilities. VLSI, 1997, Proceedings. Seventh Great Lakes Symposium on, p.2631, 1997.

K. P. Parker and E. J. Mccluskey, Probabilistic treatment of general combinational networks. Computers, IEEE Transactions, issue.6, p.24668670, 1975.

F. Brglez, On testability analysis of combinational networks. Circuits and systems, IEEE International symposium on, p.221225, 1984.

S. C. Seth, L. Pan, and V. D. , Predict-probabilistic estimation of digital circuit testability. Fault-Tolerant Computation Symposium (FTCS-15, Dig. Papers of, p.220225, 1985.

J. Savir, G. S. Ditlow, and P. H. Bardell, On random pattern test length. Computers, IEEE Transactions, issue.1, p.337990, 1984.
DOI : 10.1109/tc.1984.1676470

S. K. Jain and V. D. , Statistical Fault Analysis, IEEE Design & Test of Computers, vol.2, issue.1, p.3844, 1985.
DOI : 10.1109/MDT.1985.294683

Q. Zhou and K. Mohanram, Transistor sizing for radiation hardening, Reliability Physics Symposium Proceedings, 2004. 42nd Annual, p.310315, 2004.

D. T. Franco, J. Naviner, and L. Naviner, Convolution blocks based on selfchecking operators. Mixed Design of Integrated Circuits and Systems, MIXDES '07. 14th International Conference on, p.487491, 2007.
DOI : 10.1109/mixdes.2007.4286211

L. A. Naviner, M. C. De-vasconcelos, D. T. Franco, and J. Naviner, Ecient computation of logic circuits reliability based on probabilistic transfer matrix. Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2008. 3rd International Conference on, p.14, 2008.

D. Franco, M. Correia, L. Naviner, and J. Naviner, Reliability analysis of logic circuits based on signal probability, 2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008.
DOI : 10.1109/ICECS.2008.4674942

D. T. Maí-correia-vasconcelos, L. Franco, J. Naviner, and . Naviner, On the output events in concurrent error detection schemes, 2008.

D. T. Maí-correia-vasconcelos, L. Franco, J. Naviner, and . Naviner, Relevant metrics for evaluation of concurrent error detection schemes, 2008.

P. A. Gargini, The global route to future semiconductor technology. Circuits and Devices Magazine, IEEE, vol.18, issue.2, p.1317, 2002.

A. Allan, D. Edenfeld, . Jr, W. H. Joyner, A. B. Kahng et al., technology roadmap for semiconductors, Computer, vol.35, issue.1, p.4253, 2001.

M. Advanced, R. Initiative, and M. Nano, Technology roadmap for nanoelectronics -edition 1999 Microelectronics Advanced Research Initiative -MELARI NANO, 1999.

J. A. Hutchby, G. I. Bouriano, V. V. Zhirnov, and J. E. Brewer, Extending the road beyond cmos. Circuits and Devices Magazine, IEEE, vol.18, issue.2, p.2841, 2002.

A. Dehon and H. Naeimi, Seven Strategies for Tolerating Highly Defective Fabrication, IEEE Design and Test of Computers, vol.22, issue.4
DOI : 10.1109/MDT.2005.94

V. V. Zhirnov, J. A. Hutchby, G. I. Bourianos, and J. E. Brewer, Emerging research logic devices. Circuits and Devices Magazine, IEEE, vol.21, issue.3, p.3746, 2005.
DOI : 10.1109/mcd.2005.1438811

M. T. Bohr, Nanotechnology goals and challenges for electronic applications, IEEE Transactions On Nanotechnology, vol.1, issue.1, p.5662, 2002.
DOI : 10.1109/TNANO.2002.1005426

V. V. Zhirnov, J. A. Hutchby, G. I. Bouriano, and J. E. Brewer, Emerging research memory and logic technologies. Circuits and Devices Magazine, IEEE, vol.21, issue.3, p.4751, 2005.

J. R. Heath, P. J. Kuekes, G. S. Snider, and R. Williams, A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology, Science, vol.280, issue.5370, p.28017161721, 1998.
DOI : 10.1126/science.280.5370.1716

S. , C. Goldstein, and M. Budiu, Nanofabrics: spatial computing using molecular electronics, Proceedings. 28th Annual International Symposium on, p.178189, 2001.

M. Mishra and S. C. Goldstein, Defect tolerance at the end of the roadmap, Proceedings. ITC 2003. International, 2003.

M. M. Ziegler and M. R. Stan, CMOS/nano Co-design for crossbar-based molecular electronic systems, IEEE Transactions On Nanotechnology, vol.2, issue.4, p.217230, 2003.
DOI : 10.1109/TNANO.2003.820804

T. Hogg and G. S. Snider, Defect-tolerant adder circuits with nanoscale crossbars, IEEE Transactions On Nanotechnology, vol.5, issue.2, p.97100, 2006.
DOI : 10.1109/TNANO.2006.869684

M. Lee, Y. K. Kim, and Y. Choi, A Defect-Tolerant Memory Architecture for Molecular Electronics, IEEE Transactions On Nanotechnology, vol.3, issue.1, p.152157, 2004.
DOI : 10.1109/TNANO.2004.824011

J. M. Tour, W. L. Van-zandt, C. P. Husband, S. M. Husband, L. S. Wilson et al., Nanocell logic gates for molecular computing, IEEE Transactions On Nanotechnology, vol.1, issue.2, p.100109, 2002.
DOI : 10.1109/TNANO.2002.804744

C. P. Husband, S. M. Husband, J. S. Daniels, and J. M. Tour, Logic and memory with nanocell circuits. Electron Devices, IEEE Transactions on, vol.50, issue.9, p.18651875, 2003.
DOI : 10.1109/ted.2003.815860

K. K. Likharev, Neuromorphic CMOL circuits, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003., p.339342, 2003.
DOI : 10.1109/NANO.2003.1231787

O. Turel, J. H. Lee, X. Ma, and K. K. Likharev, Nanoelectronic neuromorphic networks (CrossNets): new results, 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541), p.394, 2004.
DOI : 10.1109/IJCNN.2004.1379937

S. Mitra, W. Huang, N. R. Saxena, S. Yu, and E. J. Mccluskey, Recongurable architecture for autonomous self-repair. Design & Test of Computers, IEEE, vol.21, issue.3, p.228240, 2004.

M. A. Breuer, Intelligible Test Techniques to Support Error-Tolerance, 13th Asian Test Symposium, p.386393, 2004.
DOI : 10.1109/ATS.2004.51

S. C. Goldstein, The impact of the nanoscale on computing systems, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., p.655661, 2005.
DOI : 10.1109/ICCAD.2005.1560148

D. P. Vasudevan and P. K. Lala, A technique for modular design of self-checking carry-select adder. Defect and Fault Tolerance in VLSI Systems, DFT 2005. 20th IEEE International Symposium on, p.325333, 2005.

G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, and A. Salsano, Error detection in signed digit arithmetic circuit with parity checker [adder example]. Defect and Fault Tolerance in VLSI Systems, Proceedings. 18th IEEE International Symposium on, p.401408, 2003.

A. Lindstrom, M. Nordseth, and L. Bengtsson, Vhdl library of nonstandard arithmetic units, 2003.

A. Lindstrom, M. Nordseth, and L. Bengtsson, Contributions to residue-number-system/signed-digit arithmetic

W. J. Townsend, J. A. Abraham, and P. K. Lala, On-line error detecting constant delay adder. On-Line Testing Symposium, IOLTS 2003. 9th IEEE, p.1722, 2003.
DOI : 10.1109/olt.2003.1214361

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.2801

D. Marienfeld, E. S. Sogomonyan, V. Ocheretnij, and M. Gossel, A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., p.3035, 2004.
DOI : 10.1109/ETSYM.2004.1347594

. Goutis, Cosafe, low power hardware-software co-design for safety-critical applications, 1999.

N. Issam-alzaher, Outils de CAO pour la Génération d'Opérateurs Arithmétiques Auto-Contrôlables, Laboratoire Techniques de l'Informatique et de la Microélectronique pour l'Architecture de l'Ordinateur (TIMA), 2001.

J. Q. Wang and P. K. Lala, Partially strongly fault secure and partially strongly code disjoint 1-out-of-3 code checker. Computers, IEEE Transactions on, issue.10, pp.431238-1240, 1994.

A. Paschalis, N. Gaitanis, D. Gizopoulos, and P. Kostarakis, A totally self-checking 1-out-of-3 code error indicator, Proceedings European Design and Test Conference. ED & TC 97, p.450, 1997.
DOI : 10.1109/EDTC.1997.582399

M. Wirthlin, N. Rollins, M. Carey, and P. Graham, Hardness by design techniques for eld programmable gate arrays, Proceedings of the 11th Annual NASA Symposium on VLSI Design

W. Steven and . Smith, The Scientist and Engineer's Guide to Digital Signal Processing, Analog Devices, 1999.

X. Wendling, H. Chauvet, L. Reveret, R. Rochet, and R. Leveugle, Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities. Defect and Fault Tolerance in VLSI Systems, IEEE International Symposium on, p.195203, 1997.