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DOI : 10.1109/MM.2007.39
ATLAS: A Chip-Multiprocessor with Transactional Memory Support, 2007 Design, Automation & Test in Europe Conference & Exhibition, 2007. ,
DOI : 10.1109/DATE.2007.364558
Design and Implementation of a Message Passing Multi-processor System on the BEE2, master thesis, 2007. ,
RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors, The 4th Workshop on Architectural Research Prototyping, 2009. ,
BEE2 A High-End Reconfigurable Computing System, IEEE Design and Test of Computers, vol.22, issue.2, pp.114-125, 2005. ,
DOI : 10.1109/MDT.2005.30
BB-762: Design and Implementation of 762 Processor Multiprocessor and OCP-IP Benchmarking, 2009. ,
Automatic Design Methodologies for Large Scale MPSOC and Prototyping on Multi-FPGA Platforms, International SoC Design Conference (ISOCC) 2009, invited talk, 2009. ,
Multi-FPGA emulation of a 48-cores multiprocessor with NOC, Design and Test Workshop, 2008. ,
An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography, International Journal of Reconfigurable Computing, vol.2009, 2009. ,
DOI : 10.1155/2008/685128
Omar Hammami; NOC Monitoring Feedback for Parallel Programmers Circuits and Systems, IEEE, 2006. ,
Omar Hammami;NOC Monitoring Hardware Support for fast NOC Design Space Exploration and Potential NOC Partial Dynamic Reconfiguration, 2006. ,
Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution , Parallel and Distributed Processing SymposiumMOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution, IPDPS EURASIP Journal of Embedded Systems, vol.1, issue.0, 2006. ,
The PARSEC Benchmark Suite: Characterization and Architectural Implications, Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008. ,
PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors, Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, 2009. ,
A 45 nm 8-Core Enterprise Xeon¯ Processor, Solid-State Circuits, IEEE Journal, pp.45-46, 2010. ,
The dawn of terascale computing, Solid-State Circuits Magazine, IEEE, issue.1s, pp.83-89, 2009. ,