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Study of the impact of variations of fabrication process on digital circuits

Abstract : Designing digital circuits for sub-100nm bulk CMOS technology faces many challenges in terms of Process, Voltage, and Temperature variations. The focus has been on interdie variations that form the bulk of process variations. In this work, we have focused on two particular kinds of variations- Inter-die NMOS to PMOS mismatch and Intra-die local random mismatch. Neither had a noticeable effect in industrial designs and has become a cause of worry only recently. The source of these variations lies in the basic process and is random in nature. Thus, their effect cannot be ameliorated without overhauling the complete process. The work in academia has mostly focused on process changes or architectural improvements. Our work is geared towards design improvements at gate and path level. We looked at the basic phenomena behind these variations and using simulations observed how they affect the different parameters in a digital design. The focus was on synchronous systems, i.e. clock distribution system that is highly impacted by these variations. We proposed some design methods and optimization strategies to make the circuits more robust. Most of these methods are exploitable within existing design flows that minimizes the cost and allows for quick adoption in the industry. We included the effect of voltage and temperature changes on these two variations to put together a comprehensive understanding. We also proposed methods to verify the basis of our work by comparing against silicon test results. The results of this work have helped to shape the policy of how to handle local mismatch in industrial designs.
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Contributor : Tarun Chawla Connect in order to contact the contributor
Submitted on : Wednesday, November 17, 2010 - 3:39:18 PM
Last modification on : Friday, July 31, 2020 - 10:44:06 AM
Long-term archiving on: : Saturday, December 3, 2016 - 12:24:43 AM


  • HAL Id : pastel-00537050, version 1



Tarun Chawla. Study of the impact of variations of fabrication process on digital circuits. Micro and nanotechnologies/Microelectronics. Télécom ParisTech, 2010. English. ⟨NNT : -⟩. ⟨pastel-00537050⟩



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