L. Benini, G. De-micheli, A. A. Morgan-kaufmann-jerraya, and G. Martin, Networks on Chips: Technology and Tools Multiprocessor System-on-Chip (MPSoC) Technology Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.27, issue.10s, pp.1701-1713, 2006.

D. Atienza, F. Angiolini, S. Murali, A. Pullini, and L. Benini, De Micheli, G, Network-on-Chip design and synthesis outlook, Integration, the VLSI Journal, pp.340-359, 2008.

U. Y. Ogras, R. Marcillescu, P. Hyung-gyu-lee-;-choudhary, D. Marculescu, M. Kaufman et al., Challenges and Promising Results in NoC Prototyping Using FPGAs Comparison of An Athereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip, Proc. IFIP Int'l Conference on Very Large Scale Integration (VLSI-SoC), pp.86-95, 2006.

A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. De-micheli et al., Bringing NoCs to 65 nm " Micro, IEEE, pp.75-85, 2007.

P. Guerrier and A. Greiner, A generic architecture for on-chip packet-switched interconnections, Proc. Design Automation and Test in Europe (DATE'00), pp.250-256, 2000.

A. Andriahantenaina and . Greiner, Micro-network for SoC: implementation of a 32-port SPIN network, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.1128-1129, 2003.
DOI : 10.1109/DATE.2003.1253766

K. Goossens, J. Van-meerbergen, A. Peeters, and P. Wielage, Networks on silicon: combining best-effort and guaranteed services, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002.
DOI : 10.1109/DATE.2002.998309

K. Goossens, J. Dielissen, and A. Radulescu, ??thereal Network on Chip:Concepts, Architectures, and Implementations, IEEE Design and Test of Computers, vol.22, issue.5, pp.414-421, 2005.
DOI : 10.1109/MDT.2005.99

K. Goossens, J. Dielissen, O. P. Gangwal, S. Gonzalez-pestana, A. Radulescu et al., A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification, Design, Automation and Test in Europe, 2005.
DOI : 10.1109/DATE.2005.11
URL : https://hal.archives-ouvertes.fr/hal-00181291

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson et al., An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp.5-7, 2007.
DOI : 10.1109/ISSCC.2007.373606

T. Bjerregaard and J. Sparso, A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip, Design, Automation and Test in Europe, 2005.
DOI : 10.1109/DATE.2005.36
URL : https://hal.archives-ouvertes.fr/hal-00181298

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture, vol.50, issue.2-3, pp.105-128, 2004.
DOI : 10.1016/j.sysarc.2003.07.004

M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1269001

A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, SPIN: a scalable, packet switched, on-chip micro-network, 2003 Design, Automation and Test in Europe Conference and Exhibition, 2003.
DOI : 10.1109/DATE.2003.1253808

T. Bjerregaard and S. Mahadevan, A survey of research and practices of Network-onchip, ACM Comput. Surv, vol.38, issue.1, 2006.

B. Senouci, M. Kouadri, A. M. Rousseau, F. Petrot, and F. , Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, pp.41-47, 2008.
DOI : 10.1109/RSP.2008.27
URL : https://hal.archives-ouvertes.fr/hal-00293652

D. Wentzlaff, P. Griffin, H. Hoffmann, B. Edwards, C. Ramey et al., On-Chip Interconnection Architecture of the Tile Processor, IEEE Micro, vol.27, issue.5, pp.15-31, 2007.
DOI : 10.1109/MM.2007.4378780

J. Shirako, M. Mase, K. Kimura, and H. Kasahara, An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler Solid-State Circuits Conference, Digest of Technical Papers. IEEE International 3-7 Feb, pp.90-598, 2008.

S. Shibahara, M. Takada, T. Kamei, K. Hayase, Y. Yoshida et al., SH-X3: SuperH Multi-Core for Embedded Systems, Hot Chips 19th, 2007.

M. Butts and A. M. Jones, TeraOPS Hardware & Software: A New Massively-Parallel, MIMD Computing Fabric IC, Hot Chips 18th, 2006.

T. Miyamori, Venezia: a Scalable Multicore Subsystem for Multimedia Applications, 8th International Forum on Application-Specific Multi-Processor SoC 23 -27 http://www.mpsoc-forum.org/ also " A Power Performance Scalable 8 cores Media Processor for Mobile Multimedia Applications, IEEE Journal of Solid State Circuits, vol.44, issue.11, 2008.

T. Isshiki and . Maps-tct, MPSoC Application Parallelization and Architecture Exploration Framework, 8th International Forum on Application-Specific Multi-Processor SoC 23 -27, 2008.

S. Kumar, Architectural Support for Fine-Grained Parallelism on Multi-core Architectures, 2007.

R. B. Mouhoub and O. Hammami, NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration " IES'06, pp.1-10, 2006.

M. Krstic, E. Grass, F. K. Gurkaynak, and P. Vivet, Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook, IEEE Design & Test of Computers, vol.24, issue.5, pp.430-441, 2007.
DOI : 10.1109/MDT.2007.164

T. Hsiao, Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems, IIHMSP, pp.19-22, 2007.

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, A 5-GHz Mesh Interconnect for a Teraflops Processor, IEEE Micro, vol.27, issue.5, pp.51-61, 2007.
DOI : 10.1109/MM.2007.4378783

S. Lukovic and L. Fiorin, An Automated Design Flow for NoC-based MPSoCs on FPGA, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, pp.58-64, 2008.
DOI : 10.1109/RSP.2008.31

T. Hsiao, Hardware-oriented Partition for Embedded Multiprocessor FPGA Systems, pp.65-65, 2007.

J. Goodacre and A. N. Sloss, Parallelism and the ARM instruction set architecture, Computer, vol.38, issue.7, pp.42-52, 2005.
DOI : 10.1109/MC.2005.239

C. Haubelt, J. Falk, J. Keinert, T. Schlichter, M. Streubühr et al., A SystemC-Based Design Methodology for Digital Signal Processing Systems, Article ID 47580, p.22, 2007.

S. Ouadjaout and D. Houzet, Generation of Embedded Hardware/Software from SystemC, EURASIP Journal on Embedded Systems, p.11, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00127973

M. O. Cheema, L. Lacassagne, and O. Hammami, System-Platforms-Based SystemC TLM Design of Image Processing Chains for Embedded Applications, EURASIP Journal on Embedded Systems, 2007.

S. Edwards, The Challenges of Synthesizing Hardware from C-Like Languages, IEEE Design & Test of Computers, vol.23, issue.5, pp.375-386, 2006.
DOI : 10.1109/MDT.2006.134

D. Galloway, The Transmogrifier C hardware description language and compiler for FPGAs, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, pp.136-144, 1995.
DOI : 10.1109/FPGA.1995.477419

K. Wakabayashi, C-based synthesis experiences with a behavior synthesizer, Cyber, Europe Conference and Exhibition 1999. Proceedings, pp.9-12, 1999.

D. Ku and G. D. Micheli, Hardware C: a language for hardware design, 2000.

T. Kambe, A. Yamada, K. Nishida, K. Okada, M. Ohnishi et al., A C-based synthesis system, Bach, and its application, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455), pp.151-155, 2001.
DOI : 10.1109/ASPDAC.2001.913296

E. Grimpe and F. Oppenheimer, Extending the SystemC synthesis subset by object-oriented features, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis , CODES+ISSS '03, 2003.
DOI : 10.1145/944650.944652

S. Gupta, N. D. Dutt, R. K. Gupta, and A. Nicolau, SPARK: a high-level synthesis framework for applying parallelizing compiler transformations, 16th International Conference on VLSI Design, 2003. Proceedings., 2003.
DOI : 10.1109/ICVD.2003.1183177

V. and S. Saun, Preeti Ranjan PandaExtracting exact finite state machines from behavioral SystemC descriptions, Proceedings of International Conference on VLSI Design, pp.280-285, 2005.

H. D. Patel, S. K. Shukla, and R. A. Bergamaschi, Heterogeneous Behavioral Hierarchy Extensions for SystemC, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.26, issue.4s, pp.765-780, 2007.

S. Chtourou and O. Hammami, SystemC Space Exploration of Behavioral Synthesis Options on Area, Performance and Power consumption, 2005 International Conference on Microelectronics, 2005.
DOI : 10.1109/ICM.2005.1590039

. Agility, asp [ 59 ] Forte Design www.forteds.com [ 60 ] Orinoco Dale http://www.chipvision.com/company/index.php [ 61 ] ImpulseC Inc " Co-developper's user guide " www.impulseC.com, Digital Image Processing, 2007.

J. Revelles, C. Urena, and M. Lastra, An efficient parametric algorithm for octree traversal, Czech Republic, 2000.

A. Http, amd.com/ZONES/BARCELONA/Pages/default.aspx [ 67 ] NoC Solution 1.12, NoC Compiler user's guide, 2008.

A. Klimm, L. Braun, and J. Becker, An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores, 2008 IEEE International Symposium on Parallel and Distributed Processing, 2008.
DOI : 10.1109/IPDPS.2008.4536519

J. Joven, O. Font-bach, D. Castells-rufas, R. Martinez, L. Teres et al., xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures, 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), pp.141-148, 2008.
DOI : 10.1109/PDP.2008.24

R. Kumar, Alpha-data ADPe-XRC-4 FPGA card http://www.alpha-data.com/adpe-xrc-4.html [ 75 ] Xilinx Virtex-4 www, Arteris Danube 1.12, Packet Transport Units technical reference, o4277v11, 2005.

F. Moraes, N. Calazans, A. Mello, L. Moller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, pp.69-93, 2004.

R. R. Hoare, Z. Ding, S. Tung, R. Melhem, and A. K. Jones, A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks, Journal of Parallel and Distributed Computing, vol.65, issue.10, pp.1237-1252, 2005.
DOI : 10.1016/j.jpdc.2005.04.022

M. Monchiero, G. Palermo, C. Silvano, and O. Villa, Exploration of distributed shared memory architectures for NoC-based multiprocessors, Journal of Systems Architecture, vol.53, issue.10, pp.719-732, 2007.
DOI : 10.1016/j.sysarc.2007.01.008

J. Daemen and V. Rijmen, The Design of Rijndael: AES -The Advanced Encryption Standard, 2002.
DOI : 10.1007/978-3-662-04722-4

P. Crowley, The future in your pocket, ACM SIGCOMM Computer Communication Review, vol.38, issue.2, 2008.
DOI : 10.1145/1355734.1355744

M. R. Rizk and M. Morsy, Optimized Area and Optimized Speed Hardware Implementations of AES on FPGA " International Design and Test Workshop, pp.207-217, 2007.

Y. Yue, C. Lin, and Z. Tan, NPCryptBench, 05: Proceedings of the 2005 workshop on MEmory performance DAC '06: Proceedings of the 43rd annual conference on Design automation ACM, 2006.
DOI : 10.1145/1147349.1147359

J. Lee, S. Yoon, K. Pyun, and S. Park, A multi-processor NoC platform applied on the 802.11i TKIP cryptosystem, ASP-DAC '08: Proceedings of the 2008 conference on Asia and South Pacific design automation, 2008.

A. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chip, 2004.
URL : https://hal.archives-ouvertes.fr/hal-01391627

A. Klimm, L. Braun, and J. Becker, An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores, 2008 IEEE International Symposium on Parallel and Distributed Processing, 2008.
DOI : 10.1109/IPDPS.2008.4536519

M. Hutton, R. Yuan, J. Schleicher, G. Baeckler, and S. Cheung, Kar Keng Chua; Hee Kong Phoon;, A Methodology for FPGA to Structured-ASIC Synthesis and Verification, DATE '06. Proceedings Volume, pp.6-10, 2006.

T. Bautista and A. Nunez, Quantitative study of the impact of design and synthesis options on processor core performance , Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Issue, vol.3, issue.9s, pp.461-473, 2001.

T. Bjerregaard and S. Mahadevan, A survey of research and practices of Network-on-chip, Computing Surveys (CSUR)

L. Benini and G. De-micheli, Networks on Chips: Technology and Tools, 2006.

. J. David, R. Frank, D. Puri, and . Toma, Design and CAD challenges in 45nm CMOS and beyond, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, 2006.

J. W. Mcpherson, Reliability challenges for 45nm and beyond, Proceedings of the 43rd annual conference on Design automation , DAC '06, 2006.
DOI : 10.1145/1146909.1146959

A. B. Kahng, Design Challenges at 65nm and Beyond, 2007 Design, Automation & Test in Europe Conference & Exhibition, 2007.
DOI : 10.1109/DATE.2007.364505

J. Kawa and C. Chiang, DFM issues for 65nm and beyond, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, 2007.
DOI : 10.1145/1228784.1228861

J. Xi and P. Zhong, A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models, Proceedings of the 16th ACM Great Lakes symposium on VLSI , GLSVLSI '06, 2006.
DOI : 10.1145/1127908.1127986

L. Singhal, S. Oh, and E. Bozorgzadeh, Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, CODES/ISSS '08, 2008.
DOI : 10.1145/1450135.1450192

M. Nowak, J. Corleto, C. Chun, and R. Radojcic, Holistic pathfinding, Proceedings of the 45th annual conference on Design automation, DAC '08, 2008.
DOI : 10.1145/1391469.1391620

J. Balfour and W. J. Dally, Design tradeoffs for tiled CMP on-chip networks, Proceedings of the 20th annual international conference on Supercomputing, 2006.

T. G. Mattson, R. Van-der-wijngaart, and M. Frumkin, Programming the Intel 80-core network-on-a-chip Terascale Processor, 2008 SC, International Conference for High Performance Computing, Networking, Storage and Analysis, 2008.
DOI : 10.1109/SC.2008.5213921

H. Wong, Pangaea, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, 2008.
DOI : 10.1145/1454115.1454125

C. Pitter, Time-predictable memory arbitration for a Java chip-multiprocessor, Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems, 2008.

H. Kong-phoon, Chuan Khye Chai; A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration, Semiconductor Electronics, pp.506-510, 2006.

J. Pistorius, M. Hutton, J. Schleicher, M. Iotov, E. Julias et al., Equivalence Verification of FPGA and Structured ASIC Implementations, Field Programmable Logic and Applications, FPL 2007. International Conference, pp.423-428, 2007.

K. Compton and S. Hauck, Automatic Design of Area-Efficient Configurable ASIC Cores, Computers, IEEE Transactions on, vol.56, issue.5s, pp.662-672, 2007.

I. Kuon and J. Rose, Measuring the Gap Between FPGAs and ASICs, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.26, issue.2s, pp.203-215, 2007.

A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. De-micheli et al., Bringing NoCs to 65 nm Micro, pp.75-85, 2007.

R. , B. Mouhoub, and O. Hammami, MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution, EURASIP Journal on Embedded Systems, vol.2006, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00847913

A. Hanson, K. Goossens, M. Bekooij, and J. Huisken, CoMPSoC, ACM Transactions on Design Automation of Electronic Systems, vol.14, issue.1, 2009.
DOI : 10.1145/1455229.1455231

E. S. Chung, ProtoFlex, ACM Transactions on Reconfigurable Technology and Systems, vol.2, issue.2, 2009.
DOI : 10.1145/1534916.1534925

D. N. Truong, A 167-Processor Computational Platform in 65 nm CMOS, IEEE Journal of Solid-State Circuits, vol.44, issue.4, pp.1130-1144, 2009.
DOI : 10.1109/JSSC.2009.2013772

P. Emma and E. Kursun, Opportunities and Challenges for 3D Systems and Their Design, IEEE Design & Test of Computers, pp.6-14, 2009.

H. Sun, 3D DRAM Design and Application to 3D Multicore Systems, IEEE Design & Test of Computers, vol.26, issue.5, pp.36-46, 2009.
DOI : 10.1109/MDT.2009.105

V. F. Pavlidis and E. G. Friedman, 3-D Topologies for Networks-on-Chip, Very Large Scale Integration (VLSI) Systems, pp.1081-1090, 2007.

B. S. Feero and P. P. Pande, Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation, IEEE Transactions on Computers, vol.58, issue.1, pp.32-45, 2009.
DOI : 10.1109/TC.2008.142

C. Batten, Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics, IEEE Micro, vol.29, issue.4, pp.8-21, 2009.
DOI : 10.1109/MM.2009.60

M. Petracca, Photonic NOCs: System Level Design Space Exploration, IEEE Micro, pp.74-84, 2009.

O. Hammami, Z. Wang, V. Fresse, and D. Houzet, A Case Study: Quantitative Evaluation of C-Based High-Level Synthesis Systems, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008.
DOI : 10.1109/MDT.2006.134

Z. Wang, O. Hammamiwang, O. Hammami, and D. Houzet, A NoC based heterogeneous Multiprocessor System on Chip Implementation " submitted Elsevier Microelectronics Journal 3 Architecture and Parallel Programming Implications of Migrating Single FPGA Chip Multiprocessor with Network on Chip to 65nm and 45nm ASIC, Performance Evaluation and Enhancement Mechanisms for Image Processing Algorithms on 16 PE NOC Based Multi-core Embedded Platform" submitted to Journal of Real-Time Image Processing Conferences papers 5

Z. Hammami, V. Wang, D. Fresse, and . Houzet, A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design, 2008 IEEE International Symposium on Circuits and Systems
DOI : 10.1109/ISCAS.2008.4541431
URL : https://hal.archives-ouvertes.fr/hal-00322712

Z. Wang and O. Hammami, C-based hardware-accelerator coprocessing for SOC an quantitative area-performance evaluation, 2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008.
DOI : 10.1109/ICECS.2008.4674905

Z. Wang, O. Hammami, and I. Soc, A Twenty-four Processors System on Chip FPGA Design with On-Chip Network Connection, 2008.

Z. Wang and O. Hammami, External DDR2-Constrained NOC-Based 24-Processors MPSOC Design and Implementation on Single FPGA, IEEE International Design and Test Workshop, 2008.

M. Khaddour, Z. Wang, and O. Hammami, Cryptography on Multiprocessor Platform (The Case of AES), Sixth IEEE International Multi-Conference on Systems, Signals and Devices SSD09

M. Khaddour, Z. Wang, and O. Hammami, Implementing Block Cipher on Multiprocessor Platform, International Conference on Multimedia Computing and Systems ICMCS 09

M. Khaddour, Z. Wang, and O. Hammami, Performance Evaluation and Analysis of Parallel Software Implementations of TDES on a16-PE Embedded Multiprocessor Platform " , IFIP network and service security conference, 2009.