S. Selmane, S. Bhasin, T. Guilley, J. Graba, and . Danger, WDDL is Protected against Setup Time Violation Attacks, 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2009.
DOI : 10.1109/FDTC.2009.40
URL : https://hal.archives-ouvertes.fr/hal-00410135

S. Guilley, L. Sauvage, J. Danger, and N. Selmane, Fault Injection Resilience, 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010.
DOI : 10.1109/FDTC.2010.15
URL : https://hal.archives-ouvertes.fr/hal-00482194

N. Bhasin and . Selmane, ? Countering Early Evaluation: An Approach Towards Robust Dual- Rail Precharge Logic, 2010.

S. P. Skorobogatov and R. J. Anderson, Optical Fault Induction Attacks . 2523 of LNCS, pp.2-12

R. Karri, K. Wu, P. Mishra, Y. And, and . Kim, Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21, issue.12, pp.1509-1517, 2002.
DOI : 10.1109/TCAD.2002.804378

M. Karpovsky, K. J. Kulikowski, A. And, and . Taubin, Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard, International Conference on Dependable Systems and Networks, 2004, 2004.
DOI : 10.1109/DSN.2004.1311880

P. Kocher, J. Jaffe, and A. B. Jun, Differential Power Analysis, CHES99, pp.388-397, 1666.
DOI : 10.1007/3-540-48405-1_25

J. Quisquater-and-d and . Samyde, ElectroMagnetic Analysis (EMA): Measures and Counter-measures for Smart Cards, LNCS Springer, vol.140, pp.200-210, 2001.
DOI : 10.1007/3-540-45418-7_17

J. Blömer and J. Seifert, Fault Based Cryptanalysis of the Advanced Encryption Standard (AES), SPRINGER, editor, Financial Cryptography, 2742 of LNCS, pp.162-181, 2003.
DOI : 10.1007/978-3-540-45126-6_12

D. Boneh, R. A. Demillo, and R. J. Lipton, On the Importance of Eliminating Errors in Cryptographic Computations, Journal of Cryptology, vol.14, issue.2, pp.101-119, 2001.
DOI : 10.1007/s001450010016

T. , K. J. Bloom, I. J. Cox, and M. L. Miller, Copy protection for DVD video, Proceedings of the IEEE, pp.1267-1276, 1999.

A. L. Shamir-r, . Rivset-and-l, and . Adleman, A method for obtaining digital signatures and public-key cryptosystems, commun. ACM, vol.21, pp.120-126, 1978.

G. , S. I. Blake, and N. P. Smart, Elliptic Curves in Cryptography, 1999.

P. C. Kocher, J. Jaffe, and A. Benjamin, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Proceedings of CRYPTO'96, 1109 of LNCS, pp.104-113, 1996.
DOI : 10.1007/3-540-68697-5_9

P. C. Kocher, J. Jaffe, and A. Benjamin, Differential Power Analysis, Proceedings of CRYPTO'99, 1666 of LNCS, pp.388-397, 1999.
DOI : 10.1007/3-540-48405-1_25

J. Samyde, ElectroMagnetic Analysis (EMA): Measures and Counter-Measures for Smard Cards, Smart Card Programming and Security (E-smart 2001), 2140 of LNCS, pp.200-210, 2001.

H. Bar-el, H. Choukri, D. Naccache, M. Tunstal, C. And et al., The Sorcerer's Apprentice Guide to Fault Attacks, Proceedings of the IEEE, pp.370-382, 2006.
DOI : 10.1109/JPROC.2005.862424

R. Fault-attacks-on and . Crt, Concrete results and prcatical countermeasures, p.3, 1996.

M. Agoyan, J. Dutertre, D. Naccache, B. Robisson, A. And et al., When Clocks Fail: On Critical Paths and Clock Faults, CARDIS, pp.182-193, 2010.
DOI : 10.1007/978-3-642-12510-2_13
URL : https://hal.archives-ouvertes.fr/emse-00505344

M. Agoyan, J. Dutertre, A. Mirbaha, D. Nac-cache, A. Ribotta et al., How to flip a bit? On-Line Testing Symposium, IEEE International, vol.0, pp.235-239, 2010.

J. Samyde, Eddy current for Magnetic Analysis with Active Sensor, 2002.

M. Otto, fault attacks and countermeasures, 2004.

C. G. Dfa-on and A. Quisquater, A Differential Fault Attack Technique against SPN Structures, with Application to the AES and KHAZAD, AES) 4th international conference CHES, 2779 of LNCS, pp.27-41, 2003.

C. Yen, Differential fault analysis on AES key schedule and some countermeasures, SPRINGER, editor, Information Security and Privacy , 2727 of LNCS, pp.118-129, 2003.

P. Dusart, G. Letourneux, and A. O. Vivolo, Differential Fault Analysis on A.E.S, Applied Cryptography and Network Security, 2846 of LNCS, pp.293-306, 2003.
DOI : 10.1007/978-3-540-45203-4_23

S. Mohammad, M. Amir, and S. Mahmoud, A Generalized Method of Differential Fault Attack Against AES Cryptosystem, pp.91-100, 2006.

M. Tunstall, . Debdeep, and . Mukhopadhyay, Differential Fault Analysis of the Advanced Encryption Standard Using a Single Fault, Report, vol.575575, 2009.
DOI : 10.1007/978-3-642-21040-2_15

B. Robisson and P. Manet, Differential Behavioral Analysis, CHES, 4727 of LNCS, pp.413-426, 2007.
DOI : 10.1007/978-3-540-74735-2_28
URL : https://hal.archives-ouvertes.fr/emse-00481468

Y. Li, K. Sakiyama, S. Gomisawa, T. Fukunaga, J. Takahashi et al., Fault Sensitivity Analysis, CHES, 6225 of Lecture Notes in Computer Science, pp.320-334, 2010.
DOI : 10.1007/978-3-642-15031-9_22

J. Takahashi, T. Fukunaga, and A. Kimihiro-yamakoshi, DFA Mechanism on the AES Key Schedule, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2007), pp.62-74, 2007.
DOI : 10.1109/FDTC.2007.13

N. H. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 2004.

S. Moriok and A. Satoh, An Optimized S-Box Circuit Architecture for Low Power AES Design, Lecture Notes in Computer Science, vol.2523, issue.6, pp.271-295, 2003.
DOI : 10.1007/3-540-36400-5_14

L. Naviner, . G. Danger, and . Duc, Application Specific Integrated Circuits, 2009.

J. Francq and O. Faurax, Security of several AES Implementations against Delay Faults, Proceedings of the 12th Nordic Workshop on Secure IT Systems, 2007.
URL : https://hal.archives-ouvertes.fr/emse-00494274

S. Drimer, T. Güneysu, C. P. And, and . Dsps, DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs, 2008 16th International Symposium on Field-Programmable Custom Computing Machines, pp.99-108, 2008.
DOI : 10.1109/FCCM.2008.42

A. Barenghi, G. Bertoni, M. Breveglieri, . Pellicioli, G. And et al., Low voltage fault attacks to AES, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2010.
DOI : 10.1109/HST.2010.5513121

G. Canivet, P. Maistn, R. Leveugle, F. Valette, J. Clédière et al., Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA, 2010 15th IEEE European Test Symposium, p.251, 2010.
DOI : 10.1109/ETSYM.2010.5512740
URL : https://hal.archives-ouvertes.fr/hal-00505094

T. Malkin, F. Standaert, M. And, and . Yung, A Comparative Cost/Security Analysis of Fault Attack Countermeasures, FDTC, 4236 of Lecture Notes in Computer Science, pp.159-172, 2006.
DOI : 10.1007/11889700_15

S. Joye, Checking Before Output May Not Be Enough Against Fault-Based Cryptanalysis, IEEE Trans. Computers, vol.49, issue.9, pp.967-970, 2000.

P. C. Kocher, Leak-resistant cryptographic indexed key update, United States Patent, vol.6539, 1999.

Y. Li, S. Gomisawa, K. Sakiyama, A. Kazuo, and . Ohta, An Information Theoretic Perspective on the Differential Fault Analysis against AES. Cryptology ePrint Archive, 2010.

G. Bertoni, L. Breveglieri, I. Koren, P. And, and . Maistri, An Efficient Hardware-Based Fault Diagnosis Scheme for AES. proceedings of DFT, pp.130-138, 2004.

G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, and A. V. Piuri, Error analysis and detection procedures for a hardware implementation of the advanced encryption standard, IEEE Transactions on Computers, vol.52, issue.4, 2003.
DOI : 10.1109/TC.2003.1190590

C. Wu, Simple error detection methods for hardware implementation of Advanced Encryption Standard, IEEE transactions on computers, vol.55, issue.6, pp.720-731, 2006.

M. Karpovsky, K. J. Kulikowski, A. And, and . Taubin, Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard, 2004.
DOI : 10.1007/1-4020-8147-2_12

P. Maistri-and-r and . Leveugle, Double-Data-Rate Computation as a Countermeasure against Fault Analysis, IEEE Transactions on Computers, vol.57, issue.11, pp.1528-1539, 2008.
DOI : 10.1109/TC.2008.149

R. Anderson, M. Yen, S. Kim, S. Lim, and A. Moon, Tamper Resistance ? a Cautionary Note RSA Speedup with Chinese Remainder Theorem Immune against Hardware Fault Cryptanalysis, Proceedings of the Second USENIX Workshop ON Electronic Commerce, pp.1-11461, 1996.

D. Boneh, R. A. Demillo, and R. J. Lipton, On the Importance of Checking Cryptographic Protocols for Faults, Proceedings of Eurocrypt'97, 1233 of LNCS, pp.37-51, 1997.
DOI : 10.1007/3-540-69053-0_4

R. Gennaro, A. Lysyanskaya, T. Malkin, S. Micali, T. And et al., Algorithmic Tamper-Proof (ATP) Security: Theoretical Foundations for Security against Hardware Tampering, TCC, 2951 of Lecture Notes in Computer Science, pp.258-277, 2004.
DOI : 10.1007/978-3-540-24638-1_15

A. Boscher, H. Handschuh, E. And, and . Trichina, Blinded Fault Resistant Exponentiation Revisited, 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pp.3-9, 2009.
DOI : 10.1109/FDTC.2009.31

A. Boscher, R. Naciri, E. And, and . Prouff, CRT RSA Algorithm Protected Against Fault Attacks, WISTP, 4462 of LNCS, pp.229-243, 2007.
DOI : 10.1007/11554868_13

E. Biham and A. Shamir, Differential fault analysis of secret key cryptosystems, CRYPTO, 1294 of LNCS, pp.513-525, 1997.
DOI : 10.1007/BFb0052259

R. P. Mcevoy, M. Tunstall, C. Whelan, C. C. Murphy, and W. P. Marnane, All-or-Nothing Transforms as a countermeasure to differential side-channel analysis, International Journal of Information Security, vol.94, issue.2, 2009.
DOI : 10.1007/s10207-013-0212-y

R. P. Mcevoy, M. Tunstall, C. Whelan, C. C. Murphy, and W. P. Marnane, A differential side-channel analysis countermeasure, European Patent Application (EP 2148462 A1), 2010.

M. Medwed, F. Standaert, J. Grossschädl, F. And, and . Regazzoni, Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices, AFRICACRYPT, 6055 of LNCS, pp.279-296
DOI : 10.1007/978-3-642-12678-9_17

J. Mandal, PSS Is Secure against Random Fault Attacks, ASIACRYPT, 5912 of LNCS, pp.653-666, 2009.

S. Bhasin, T. Chouta, G. Duc, J. Danger, A. El-aabid et al., Combined countermeasures against perturbation & observation attacks, PASTIS (PAca Security Trends In embedded Security), Gardanne (École des Mines de Saint-Étienne), 2010.

Y. Baba, A. Miyamoto, N. Homma, T. And, and . Aoki, Multiple-Valued Constant-Power Adder for Cryptographic Processors, 2009 39th International Symposium on Multiple-Valued Logic, pp.239-244, 2009.
DOI : 10.1109/ISMVL.2009.9

S. Moore, R. Mullins, P. Cunningham, R. Anderson, G. And et al., Improving smart card security using self-timed circuits, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems, pp.211-218, 2002.
DOI : 10.1109/ASYNC.2002.1000311

S. W. Moore, R. J. Anderson, R. D. Mullins, G. S. Taylor, and J. J. Fournier, Balanced self-checking asynchronous logic for smart card applications, Microprocessors and Microsystems, vol.27, issue.9, pp.421-430, 2003.
DOI : 10.1016/S0141-9331(03)00092-9

N. Selmane, S. Bhasin, T. Sylvain-guilley, A. Graba, . Jean-luc et al., WDDL is Protected against Setup Time Violation Attacks, 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pp.73-83, 2009.
DOI : 10.1109/FDTC.2009.40
URL : https://hal.archives-ouvertes.fr/hal-00410135

Y. Monnet, M. Renaudin, R. Leveugle, C. Clavier, P. And et al., Case Study of a Fault Attack on Asynchronous DES Crypto-Processors, FDTC, 4236 of Lecture Notes in Computer Science, pp.88-97, 2006.
DOI : 10.1007/11889700_9
URL : https://hal.archives-ouvertes.fr/hal-00143431

S. Mangard, E. Oswald, T. And, and . Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards, 2006.

D. Sokolov, J. M. , A. Bystrov, A. And, and . Yakovlev, Design and Analysis of Dual-Rail Circuits for Security Applications, IEEE Transactions on Computers, vol.54, issue.4, pp.449-460, 2005.
DOI : 10.1109/TC.2005.61

J. Danger, S. Sylvain-guilley, A. Bhasin, C. Maxime-nassar, . Giraud et al., Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation- Level Attacks on Hardware Cryptoprocessors, ? New Attacks and Improved Counter- Measures ? A Survey on Fault Attacks, KLUWER, editor, CARDIS, pp.1-8, 2004.

D. Suzuki and M. Saeki, Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style, CHES, 4249 of LNCS, pp.255-269
DOI : 10.1007/11894063_21

K. J. Kulikowski, M. G. Karpovsky, A. And, and . Taubin, Power Attacks on Secure Hardware Based on Early Propagation of Data, 12th IEEE International On-Line Testing Symposium (IOLTS'06), pp.131-138, 2006.
DOI : 10.1109/IOLTS.2006.49

K. Tiri and I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.246-251, 2004.
DOI : 10.1109/DATE.2004.1268856

Y. Ishai, M. Prabhakaran, A. Sahai, D. And, and . Wagner, Private Circuits II: Keeping Secrets in Tamperable Circuits, EUROCRYPT, 4004 of Lecture Notes in Computer Science, pp.308-327, 2006.
DOI : 10.1007/11761679_19

R. Leveugle, Early Analysis of Fault-based Attack Effects in Secure Circuits, IEEE Transactions on Computers, vol.56, issue.10, pp.1431-1434, 2007.
DOI : 10.1109/TC.2007.1078
URL : https://hal.archives-ouvertes.fr/hal-00178989

F. Regazzoni, T. Eisenbarth, J. Grossschädl, L. Breveglieri, P. Ienne et al., Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), pp.508-516, 2007.
DOI : 10.1109/DFT.2007.61

V. Maingot and R. Leveugle, Influence of error detecting or correcting codes on the sensitivity to DPA of an AES S-box, 2009 3rd International Conference on Signals, Circuits and Systems (SCS), pp.1-5, 2009.
DOI : 10.1109/ICSCS.2009.5412600
URL : https://hal.archives-ouvertes.fr/hal-00469823

M. G. Karpovsky, K. J. Kulikowski, A. And, and . Taubin, Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard, International Conference on Dependable Systems and Networks, 2004, pp.93-101, 2004.
DOI : 10.1109/DSN.2004.1311880

K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang et al., A side-channel leakage free coprocessor IC in 0.18 µm CMOS for Embedded AES-based Cryptographic and Biometric Processing, DAC, pp.222-227, 2005.

T. Popp, M. Kirschbaum, T. Zefferer, S. And, and . Mangard, Evaluation of the Masked Logic Style MDPL on a Prototype Chip, CHES, 4727 of LNCS, pp.81-94, 2007.
DOI : 10.1007/978-3-540-74735-2_6

R. Soares, N. Calazans, V. Lomné, P. M. , L. Tor-res et al., Evaluating the robustness of secure triple track logic through prototyping, Proceedings of the twenty-first annual symposium on Integrated circuits and system design, SBCCI '08, pp.193-198, 2008.
DOI : 10.1145/1404371.1404425
URL : https://hal.archives-ouvertes.fr/lirmm-00373516

R. Soares, N. Calazans, V. Lomne, T. Ordas, P. Mau-rine et al., Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA, DATE, track A4 (Secure embedded implementations ), pp.634-639, 2009.
URL : https://hal.archives-ouvertes.fr/lirmm-00372847

S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, J. And et al., CMOS structures suitable for secured hardware, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.1414-1415, 2004.
DOI : 10.1109/DATE.2004.1269113

S. Guilley, S. Chaudhuri, L. Sauvage, P. Hoogvorst, R. Pacalet et al., Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks, IEEE Transactions on Computers, vol.57, issue.11, pp.1482-1497, 2008.
DOI : 10.1109/TC.2008.109

S. Guilley, F. Flament, R. Pacalet, P. Hoogvorst, Y. And et al., Security Evaluation of a Balanced Quasi-Delay Insensitive Library, DCIS Session 5D ? Reliable and Secure Architectures, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00283405

S. Guilley, L. Sauvage, F. Flament, P. Hoogvorst, R. And et al., Evaluation of Power-Constant Dual-Rail Logics Counter- Measures against DPA with Design-Time Security Metrics, IEEE Transactions on Computers, vol.9, issue.59, pp.1250-1263, 2010.

M. Nassar, S. Bhasin, J. Danger, G. Duc, A. Syl-vain et al., BCDL: A high performance balanced DPL with global precharge and without early-evaluation, DATE'10, pp.849-854, 2010.

J. Danger and . Sylvain-guilley, Circuit de cryptographie programmable ? Logique BCDL (Balanced Cell-based Differential Logic), 25 Mars, Institut, 2008.

S. Guilley, S. Chaudhuri, L. Sauvage, J. Danger, T. Beyrouthy et al., Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks, 2009 16th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2009), pp.351-354, 2009.
DOI : 10.1109/ICECS.2009.5411008
URL : https://hal.archives-ouvertes.fr/hal-00472064

Z. C. Yu, S. B. Furber, L. A. And, and . Plana, An investigation into the security of self-timed circuits, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings., pp.206-215, 2003.
DOI : 10.1109/ASYNC.2003.1199180

Z. Chen and Y. Zhou, Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage, CHES, 4249 of LNCS, pp.242-254
DOI : 10.1007/11894063_20

R. P. Springer, C. C. Mcevoy, W. P. Murphy, A. Marnane, and . Michael-tun-stall, Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs, ACM Trans. Reconfigurable Technol. Syst. (TRETS), vol.2, issue.1, pp.1-23, 2006.

A. Moradi, T. Eisenbarth, A. Poschmann, C. Rolfes, C. Paar et al., Information Leakage of Flip-Flops in DPA-Resistant Logic Styles, Cryptology ePrint Archive Report, vol.188, 2008.

N. Fips, . Federal, . Information, and . Standards, PUBLICATION 140-2. Security Requirements for Cryptographic Modules, p.69, 2001.

N. Fips, . Federal, . Information, and . Standards, PUBLICATION 140-3. Security Requirements for Cryptographic Modules (Draft, Revised), p.63, 2009.

S. Mangard, N. Pramstaller, E. And, and . Oswald, Successfully Attacking Masked AES Hardware Implementations, Proceedings of CHES'05, 3659 of LNCS, pp.157-171, 2005.
DOI : 10.1007/11545262_12

S. Guilley, L. Sauvage, J. Danger, T. Graba, Y. And et al., Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs, 2008 Second International Conference on Secure System Integration and Reliability Improvement, pp.16-23, 2008.
DOI : 10.1109/SSIRI.2008.31
URL : https://hal.archives-ouvertes.fr/hal-00259153

N. Selmane, A. Sylvain-guilley, . Jean-luc, and . Danger, Setup Time Violation Attacks on AES The seventh European Dependable Computing Conference, EDCC, pp.91-96, 2008.

F. Khelil, M. Hamdi, J. Sylvain-guilley, . Danger, N. And et al., Fault Analysis Attack on an FPGA AES Implementation, 2008 New Technologies, Mobility and Security, pp.1-5, 2008.
DOI : 10.1109/NTMS.2008.ECP.45

V. Maingot, J. Ferron, R. Leveugle, V. Pouget, A. And et al., Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results, Microelectronics Reliability, vol.47, issue.9-11, pp.9-111836, 2007.
DOI : 10.1016/j.microrel.2007.07.074
URL : https://hal.archives-ouvertes.fr/hal-00184528

G. Torrens, B. Alorda, S. Barceló, J. L. Rosselló, S. Bota et al., An SRAM SEU Hardening Technique for Multi-Vt Nanometric CMOS Technologies, DCIS, 2008.

J. Samyde, Radio Frequency Attacks, Encyclopedia of Cryptography and Security, 2005.

F. Vargas, D. L. Cavalcante, E. Gatti, D. Prestes, and A. D. Lupi, On the proposition of an EMI-based fault injection approach, 11th IEEE International On-Line Testing Symposium, pp.207-208, 2005.
DOI : 10.1109/IOLTS.2005.47