A. Kajiwara and M. Nakagawa, A new pll frequency synthesizer with high switching speed. Vehicular Technology, IEEE Transactions on, vol.41, issue.4, p.407413, 1992.
DOI : 10.1109/25.182591

J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors. Solid-State Circuits, IEEE Journal, vol.30, issue.4, p.412422, 1995.

R. B. Staszewski, K. Muhammad, D. Leipold, C. Hung, Y. Ho et al., All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol.39, issue.12, p.3922782291, 2004.
DOI : 10.1109/JSSC.2004.836345

J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A wide power supply range, wide tuning range, all static cmos all digital pll in 65 nm soi. Solid-State Circuits, IEEE Journal, vol.43, issue.1, p.4251, 2008.

R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep- Submicron CMOS, 2006.
DOI : 10.1002/0470041951

R. B. Staszewski, C. Fernando, and P. T. Balsara, Event-driven simulation and modeling of phase noise of an rf oscillator. Circuits and Systems I : Regular Papers, IEEE Transactions on, vol.52, issue.4, p.723733, 2005.

A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, IEEE Journal of Solid-State Circuits, vol.33, issue.2, p.179194, 1998.

A. Abidi, Phase Noise and Jitter in CMOS Ring Oscillators, IEEE Journal of Solid-State Circuits, vol.41, issue.8, p.4118031816, 2006.
DOI : 10.1109/JSSC.2006.876206

M. D. Hershenson, A. Hajimiri, S. S. Mohan, S. P. Boyd, and T. H. Lee, Design and optimization of lc oscillators Digest of Technical Papers, Computer-Aided Design IEEE/ACM International Conference on, p.6569, 1999.

W. S. Yan and H. C. Luong, A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator, Circuits and Systems II : Analog and Digital Signal Processing
DOI : 10.1109/82.917794

Y. Ou, N. Barton, R. Fetche, N. Seshan, T. Fiez et al., Phase noise simulation and estimation methods : a comparative study. Circuits and Systems II : Analog and Digital Signal Processing, IEEE Transactions on, issue.9, pp.49635-638, 2002.

A. Hajimiri, S. , and T. H. Lee, Jitter and phase noise in ring oscillators, IEEE Journal of Solid-State Circuits, vol.34, issue.6, p.790804, 1999.
DOI : 10.1109/4.766813

D. Ham and A. Hajimiri, Concepts and methods in optimization of integrated LC VCOs, IEEE Journal of Solid-State Circuits, vol.36, issue.6, p.896909, 2001.
DOI : 10.1109/4.924852

J. D. Van-der-tang, D. Kasperkovitz, and A. Van-roermund, A 9.8-11.5-ghz quadrature ring oscillator for optical receivers. Solid-State Circuits, IEEE Journal, vol.37, issue.3, pp.438-442, 2002.

M. Grozing, B. Phillip, and M. Berroth, CMOS ring oscillator with quadrature outputs and 100 MHz to 3.5 GHz tuning range, ESSCIRC 2004, 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), 2003.
DOI : 10.1109/ESSCIRC.2003.1257226

Y. A. Eken and J. P. Uyemura, The design of a 14 ghz i/q ring oscillator in 0.18 µm cmos, Circuits and Systems Proceedings of the 2004 International Symposium on, p.1336, 2004.

O. Nizhnik, R. K. Pokharel, H. Kanaya, and K. Yoshida, Low Noise Wide Tuning Range Quadrature Ring Oscillator for Multi-Standard Transceiver, IEEE Microwave and Wireless Components Letters, vol.19, issue.7
DOI : 10.1109/LMWC.2009.2022137

.. Dco-design, 70 3.2.1 Choice of DCO architecture Design of inverter based ring oscillators, p.73

O. The-interpolative, 74 3.2.2.1 5-3 Interpolative oscillator, p.76

J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors. Solid- State Circuits, IEEE Journal, vol.30, issue.4, p.412422, 1995.

R. B. Staszewski, K. Muhammad, D. Leipold, C. Hung, Y. Ho et al., All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol.39, issue.12, p.3922782291, 2004.
DOI : 10.1109/JSSC.2004.836345

J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A wide power supply range, wide tuning range, all static cmos all digital pll in 65 nm soi. Solid-State Circuits, IEEE Journal, vol.43, issue.1, p.4251, 2008.

K. Lee, . Seung-hun, Y. Jung, C. Kim, S. Kim et al., A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops, 2005 IEEE Asian Solid-State Circuits Conference, p.365368, 2005.
DOI : 10.1109/ASSCC.2005.251741

J. P. Jansson, A. Mantyniemi, and J. Kostamovaara, A CMOS Time-to-Digital Converter With Better Than 10 ps Single-Shot Precision, IEEE Journal of Solid-State Circuits, vol.41, issue.6, p.4112861296, 2006.
DOI : 10.1109/JSSC.2006.874281

R. G. Baron, The Vernier Time-Measuring Technique, Proceedings of the IRE, p.30, 1957.
DOI : 10.1109/JRPROC.1957.278252

B. Garlepp, A portable digital dll for high-speed cmos interface circuits. Solid- State Circuits, IEEE Journal, vol.34, issue.34, p.632644, 1999.

L. Sun and T. Kwasniewski, A 1.25 0.35µm monolithic cmos pll based on a multiphase ring oscillator. Solid-State Circuits, IEEE Journal, vol.36, issue.6, p.910916, 2001.
URL : https://hal.archives-ouvertes.fr/in2p3-00420482

F. H. Gebara, J. D. Schaub, A. J. Drake, K. J. Nowka, and R. B. Brown, 4.0GHz 0.18µm CMOS PLL based on an interpolate oscillator, VLSI Circuits Digest of Technical Papers. 2005 Symposium on, p.100103, 2005.

T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, United States of America, 2004.
DOI : 10.1017/CBO9780511817281

R. Best, Phase-locked loops: theory, design, and applications, 1984.

R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep- Submicron CMOS, 2006.
DOI : 10.1002/0470041951

M. Bram-de and M. Steyaert, CMOS Fractional-N synthesizer design for high spectral purity and monolithic integration, 2003.

F. William and . Egan, Phase-lock basics, 1998.

R. B. Staszewski, D. Leipold, and P. T. Balsara, Direct frequency modulation of an adpll for bluetooth/gsm with injection pulling elimination. Circuits and Systems II: Express Briefs, IEEE Transactions on, issue.6, p.52339343, 2005.

D. Ham and A. Hajimiri, Concepts and methods in optimization of integrated LC VCOs, IEEE Journal of Solid-State Circuits, vol.36, issue.6, p.896909, 2001.
DOI : 10.1109/4.924852

J. Craninckx and M. Steyaert, Low-noise voltage-controlled oscillators using enhanced lc-tanks. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, issue.12, p.42794804, 1995.

M. D. Hershenson, A. Hajimiri, S. S. Mohan, S. P. Boyd, and T. H. Lee, Design and optimization of lc oscillators Digest of Technical Papers, Computer-Aided Design IEEE/ACM International Conference on, p.6569, 1999.

J. Craninckx and M. S. Steyaert, A 1.8-ghz low-phase-noise cmos vco using optimized hollow spiral inductors. Solid-State Circuits, IEEE Journal, vol.32, issue.5, p.736744, 1997.

. Shih-an, P. R. Yu, and . Kinget, Scaling lc oscillators in nanometer cmos technologies to a smaller area but with constant performance. Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.56, issue.5, p.354358, 2009.

B. Soltanian and P. R. Kinget, Tail current-shaping to improve phase noise in lc voltage-controlled oscillators. Solid-State Circuits, IEEE Journal, issue.8, p.4117921802, 2006.

T. C. Weigandt, B. Kim, and P. R. Gray, Analysis of timing jitter in CMOS ring oscillators, Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS '94, p.2730, 1994.
DOI : 10.1109/ISCAS.1994.409188

W. S. Yan and H. C. Luong, A 900-mhz cmos low-phase-noise voltage-controlled ring oscillator. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.48, issue.2, p.216221, 2001.
DOI : 10.1109/82.917794

J. A. Mcneill, Jitter in ring oscillators. Solid-State Circuits, IEEE Journal, vol.32, issue.6, p.870879, 1997.

R. B. Staszewski, C. Hung, D. Leipold, and P. T. Balsara, A rst multigigahertz digitally controlled oscillator for wireless applications. Microwave Theory and Techniques, IEEE Transactions on, issue.11, p.5121542164, 2003.

T. H. Lee and A. Hajimiri, Oscillator phase noise: a tutorial. Solid-State Circuits, IEEE Journal, vol.35, issue.3, p.326336, 2000.
DOI : 10.1109/4.826814

URL : http://authors.library.caltech.edu/6718/1/LEEieeejssc00.pdf

D. B. Leeson, A simple model of feedback oscillator noise spectrum, Proceedings of the IEEE, p.329330, 1966.
DOI : 10.1109/PROC.1966.4682

A. Hajimiri and T. H. Lee, Design issues in cmos dierential lc oscillators. Solid-State Circuits, IEEE Journal, vol.34, issue.5, p.717724, 1999.
DOI : 10.1109/4.760384

URL : http://authors.library.caltech.edu/4915/1/HAJieeejssc99b.pdf

P. Andreani and A. Fard, More on the 1/f 2 phase noise performance of cmos dierential-pair lc-tank oscillators. Solid-State Circuits, IEEE Journal, issue.12, p.4127032712, 2006.

D. Xie and L. Forbes, Phase noise on a 2-ghz cmos lc oscillator. Computer- Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.19, issue.7, pp.773-778, 2000.

L. Devito, J. Newton, R. Croughwell, J. Bulzacchelli, and F. Benkley, A 52MHz And 155MHz Clock-recovery PLL, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p.142306, 1991.
DOI : 10.1109/ISSCC.1991.689101

A. W. Buchwald, K. W. Martin, A. K. Oki, and K. W. Kobayashi, A 6-ghz integrated phase-locked loop using algaas/gaas heterojunction bipolar transistors. Solid-State Circuits, IEEE Journal, issue.12, p.2717521762, 1992.
DOI : 10.1109/4.173102

M. Horowitz, A. Chan, J. Cobrunson, J. Gasbarro, T. Lee et al., PLL design for a 500 MB/s interface, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, p.160161, 1993.
DOI : 10.1109/ISSCC.1993.280015

M. Z. Straayer and M. H. Perrott, A 12-bit, 10-mhz bandwidth, continuous-time sigmadelta adc with a 5-bit, 950-ms/s vco-based quantizer. Solid-State Circuits, IEEE Journal, vol.43, issue.4, p.805814, 2008.

A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, IEEE Journal of Solid-State Circuits, vol.33, issue.2, p.179194, 1998.

A. Hajimiri, S. Limotyrakis, and T. H. Lee, Phase noise in multi-gigahertz CMOS ring oscillators, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143), p.4952, 1998.
DOI : 10.1109/CICC.1998.694905

A. Hajimiri, S. , and T. H. Lee, Jitter and phase noise in ring oscillators, IEEE Journal of Solid-State Circuits, vol.34, issue.6, p.790804, 1999.
DOI : 10.1109/4.766813

L. Dai and R. Harjani, Design of low-phase-noise cmos ring oscillators. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.49, issue.5, pp.328-338, 2002.

S. K. Magierowski and S. Zukotynski, Cmos lc-oscillator phase-noise analysis using nonlinear models. Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.51, issue.4, p.664677, 2004.
DOI : 10.1109/tcsi.2004.826209

F. Herzel and B. Razavi, A study of oscillator jitter due to supply and substrate noise. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.46, issue.1, p.5662, 1999.

A. Demir, Phase noise in oscillators, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design , ICCAD '98, p.170177, 1998.
DOI : 10.1145/288548.288602

S. Levantino, A. Zanchi, A. Bonfanti, and C. Samori, General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL, Southwest Symposium on Mixed Signal Design, p.3237, 2001.

R. B. Staszewski, C. Hung, N. Barton, M. Lee, and D. Leipold, A digitally controlled oscillator in a 90 nm digital cmos process for mobile phones. Solid-State Circuits, IEEE Journal, issue.11, p.4022032211, 2005.

S. Akhtar, M. Ipek, J. Lin, R. B. Staszewski, and P. Litmanen, Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS, IEEE Custom Integrated Circuits Conference 2006, p.129132, 2006.
DOI : 10.1109/CICC.2006.320849

A. E. Stevens, R. P. Van-berg, J. Van-der-spiegel, and H. H. Williams, A time-to-voltage converter and analog memory for colliding beam detectors. Solid-State Circuits, IEEE Journal, issue.6, p.2417481752, 1989.

C. Chen, P. Chen, C. Hwang, and W. Chang, A precise cyclic cmos time-todigital converter with low thermal sensitivity, Nuclear Science IEEE Transactions on, vol.52, issue.4, p.834838, 2005.

P. Chen, J. Zheng, and C. Chen, A monolithic vernier-based timeto-digital converter with dual plls for self-calibration, Custom Integrated Circuits Conference Proceedings of the IEEE 2005, p.321324, 2005.

P. Dudek, S. Szczepanski, and J. V. Hateld, A high-resolution CMOS time-todigital converter utilizing a vernier delay line, IEEE Journal of Solid-State Circuits, vol.35, issue.2, p.240247, 2000.

M. S. Gorbics, J. Kelly, K. M. Roberts, and R. L. Sumner, A high resolution multihit time to digital converter integrated circuit, Nuclear Science IEEE Transactions on, vol.44, issue.3, p.379384, 1997.

C. Hwang, P. Chen, and H. Tsao, A high-precision time-to-digital converter using a two-level conversion scheme, Nuclear Science IEEE Transactions on, vol.51, issue.4, p.13491352, 2004.

S. Kleinfelder, J. T. Majors, K. A. Blumer, W. Farr, and B. Manor, MTD132-a new subnanosecond multi-hit CMOS time-to-digital converter, IEEE Transactions on Nuclear Science, vol.38, issue.2, p.97101, 1991.
DOI : 10.1109/23.289279

R. B. Staszewski, D. Leipold, C. Hung, and P. T. Balsara, TDC-based frequency synthesizer for wireless applications, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers, p.215218, 2004.
DOI : 10.1109/RFIC.2004.1320575

J. Song, Q. An, and S. Liu, A high-resolution time-to-digital converter implemented in eld-programmable-gate-arrays. Nuclear Science, IEEE Transactions on, vol.53, issue.1, p.236241, 2006.

Y. Arai and M. Ikeno, A time digitizer cmos gate-array with a 250 ps time resolution. Solid-State Circuits, IEEE Journal, issue.2, p.31212220, 1996.

M. Lee and A. A. Abidi, A 9b, 1.25ps resolutilon coarse-ne time-to-digital converter in 90nm cmos that amplies a time residue, p.769777, 2008.

M. E. Heidari, M. Lee, and A. A. Abidi, All-digital outphasing modulator for a software-dened transmitter. Solid-State Circuits, IEEE Journal, vol.44, issue.4, p.12601271, 2009.

Y. Arai and T. Baba, A CMOS time to digital converter VLSI for high-energy physics, Symposium on VLSI Circuits, p.121122, 1998.
DOI : 10.1109/VLSIC.1988.1037453

S. Dondi, R. Strandberg, M. Nilsson, A. Boni, and P. Andreani, High-level design ow for all-digital plls, Norchip Conference, p.247250, 2006.
DOI : 10.1109/norchp.2006.329221

R. B. Staszewski, C. Fernando, and P. T. Balsara, Event-driven simulation and modeling of phase noise of an rf oscillator. Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.52, issue.4, p.723733, 2005.

E. Christen and K. Bakalar, VHDL-AMS-a hardware description language for analog and mixed-signal applications. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, issue.10, p.4612631272, 1999.

D. Lee, J. D. Villasenor, W. Luk, and P. H. Leong, A hardware gaussian noise generator using the box-muller method and its error analysis. Computers, IEEE Transactions on, issue.6, p.55659671, 2006.

A. Hajimiri and T. Lee, The Design of Low-Noise Oscillators, 1999.

S. Liu, J. Chen, L. Cai, and D. Xu, A cmos digital pll with improved locking, Solid-State and Integrated Circuits Technology Proceedings. 7th International Conference on, p.15081511, 2004.

A. Abidi, Phase Noise and Jitter in CMOS Ring Oscillators, IEEE Journal of Solid-State Circuits, vol.41, issue.8, p.4118031816, 2006.
DOI : 10.1109/JSSC.2006.876206

L. Bisdounis, S. Nikolaidis, and O. Loufopavlou, Propagation delay and short-circuit power dissipation modeling of the cmos inverter. Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol.45, issue.3, p.259270, 1998.

B. Lai and R. Walker, A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p.144145, 1991.
DOI : 10.1109/ISSCC.1991.689102

W. Chan, A 622-mhz interpolating ring vco with temperature compensation and jitter analysis, IEEE International Symposium on Circuits and Systems, p.2528, 1997.

O. Nizhnik, R. K. Pokharel, H. Kanaya, and K. Yoshida, Interpolating ring vco with v-to-f linearity compensation, Electronics Letters IEEE, issue.24, p.3020032004, 1994.

A. A. Abidi and S. Samadian, Phase noise in inverter-based and dierential cmos ring oscillators, Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005, p.457460, 2005.

Y. Ou, N. Barton, R. Fetche, N. Seshan, T. Fiez et al., Phase noise simulation and estimation methods: a comparative study. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, issue.9, pp.49635-638, 2002.

D. , G. Holmes, and T. Lipo, Pulse width modulation for power converters, 2003.
DOI : 10.1109/9780470546284

R. T. Baird and T. S. Fiez, A low oversampling ratio 14-b 500-khz adc with a selfcalibrated multibit dac. Solid-State Circuits, IEEE Journal, issue.3, p.31312320, 1996.

L. Wang, Y. Fukatsu, and K. Watanabe, A CMOS R-2R ladder digital-to-analog converter and its characterization, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188), pp.1026-1031, 2001.
DOI : 10.1109/IMTC.2001.928235

J. D. Van-der-tang, D. Kasperkovitz, and A. Van-roermund, A 9.8-11.5-ghz quadrature ring oscillator for optical receivers. Solid-State Circuits, IEEE Journal, vol.37, issue.3, pp.438-442, 2002.

M. Grozing, B. Phillip, and M. Berroth, CMOS ring oscillator with quadrature outputs and 100 MHz to 3.5 GHz tuning range, ESSCIRC 2004, 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705), p.679682, 2003.
DOI : 10.1109/ESSCIRC.2003.1257226

Y. A. Eken and J. P. Uyemura, The design of a 14 ghz i/q ring oscillator in 0.18 µm cmos, Circuits and Systems Proceedings of the 2004 International Symposium on, p.1336, 2004.

O. Nizhnik, R. K. Pokharel, H. Kanaya, and K. Yoshida, Low noise wide tuning range quadrature ring oscillator for multi-standard transceiver. Microwave and Wireless Components Letters, IEEE, issue.7, p.19470472, 2009.
DOI : 10.1109/lmwc.2009.2022137