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Conversion analogique numérique Sigma Delta reconfigurable à entrelacement temporel

Abstract : Nowadays, communication devices are supporting an increasing number of standards. The diversity of the requirements in terms of speed and resolution, makes the design of a single low power analog to digital converter (ADC) suitable for all the scenarios very problematic. Reconfigurable ADCs are a solution to this problem, where resolution would be exchanged for bandwidth. Classical Delta Sigma ADCs offer an easy way to perform this exchange by adjusting their oversampling ratios. However, they are not suitable for wideband applications. Parallelizing Delta Sigma ADCs overcomes this problem and in addition, increases the reconfigurability of the ADC. In this work, a fully reconfigurable Time-interleaved Delta Sigma ADC is proposed. Its reconfigurability permits it to perform resolution-bandwidth trade-off as well as power consumptionbandwidth trade-off by adjusting the operation frequency, the number of active channels, the oversampling ratio and the modulator order. A novel interpolation technique is also proposed. It allows to downscale the capacitor sizes that may otherwise reach unreasonable values if large resolutions are required and relaxes the constraints on the anti-alias filter as well. A prototype of the presented Time-interleaved Delta Sigma ADC has been realized in a 1.2 V 65 nm CMOS technology. It was designed to fulfill the requirements of GSM, EDGE, UMTS, DVBT, WiFi and WiMax standards. For the GSM/EDGE scenario, a 80 dB SNR was measured. For the rest of scenarios, the performances were not secured but the functionality was tested successfully.
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Contributor : Chadi Jabbour <>
Submitted on : Tuesday, July 19, 2011 - 4:15:23 PM
Last modification on : Friday, October 16, 2020 - 12:26:28 AM
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  • HAL Id : pastel-00609650, version 1

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Chadi Jabbour. Conversion analogique numérique Sigma Delta reconfigurable à entrelacement temporel. Electronics. Télécom ParisTech, 2010. English. ⟨pastel-00609650⟩

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