S. Norsworthy, R. Schreier, and G. Temes, Delta-sigma data converters, Theory, design and simulation, 1997.
DOI : 10.1109/9780470544358

R. Schreier and G. C. Temes, Understanding Delta-sigma data converters, 2005.
DOI : 10.1002/9781119258308

A. Eshraghi and T. Fiez, A time-interleaved parallel ????D converter, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, issue.3, pp.118-129, 2003.
DOI : 10.1109/TCSII.2003.810488

I. Galton and H. T. Jensen, Delta-Sigma modulator based A/D conversion without oversampling, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.42, issue.12, pp.773-784, 1995.
DOI : 10.1109/82.476175

R. Khoini-poorfard and D. , Time-interleaved oversampling convertors, Electronics Letters, vol.29, issue.19, pp.1673-1674, 1993.
DOI : 10.1049/el:19931112

P. Aziz, H. Sorensen, and J. Van, Multiband sigma-delta modulation, Electronics Letters, vol.29, issue.9, pp.760-762, 1993.
DOI : 10.1049/el:19930509

G. Gielen and W. Dehaene, Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?, Design, Automation and Test in Europe, 2005.
DOI : 10.1109/DATE.2005.64
URL : https://hal.archives-ouvertes.fr/hal-00181492

C. Jabbour, D. Camarero, V. T. Nguyen, and P. Loumeau, Optimizing the Number of Channels for Time-Interleaved Sample-and-Hold Circuits. Newcas-Taisa, pp.245-248, 2008.

C. Jabbour, V. T. Nguyen, and P. Loumeau, A Technique to Reduce the Impact of Hysterisys in Delta Sigma Analog to Digital Converters, IEEE International Symposium on Circuits and Systems, 2010.

C. Jabbour, V. T. Nguyen, and P. Loumeau, A New Interpolation Technique for TI Delta Sigma A/D Converters, IEEE International Symposium on Circuits and Systems, 2010.

A. Beydoun, C. Jabbour, V. T. Nguyen, and P. Loumeau, An Oversampled TI Delta Sigma ADC. Submitted to Analog Integrated Circuits and Signal Processing, 2010.

H. Fakhoury, C. Jabbour, H. Khushk, V. T. Nguyen, and P. Loumeau, A 65nm CMOS EDGE/UMTS/WLAN Tri-Mode Four-Channel Time-Interleaved SD ADC, 2009.
DOI : 10.1109/newcas.2009.5290508

A. Beydoun, C. Jabbour, H. Fakhoury, V. T. Nguyen, L. Naviner et al., A 65 nm CMOS Versatile ADC using Time Interleaving and ?? modulation for Multi-mode Receiver, 2009.

C. Jabbour, D. Camarero, V. T. Nguyen, and P. Loumeau, A 1 V 65 nm CMOS Reconfigurable Time Interleaved High Pass Delta Sigma ADC, IEEE International Symposium on Circuits and Systems, pp.1557-1560, 2009.

C. Jabbour, V. T. Nguyen, and P. Loumeau, A Complete Review of Cmos Switch Operation . Submitted to Analog Integrated Circuits and Signal Processing, 2010.

W. Black and D. Hodges, Time interleaved converter arrays, IEEE Journal of Solid-State Circuits, vol.15, issue.6, pp.1022-1029, 1980.
DOI : 10.1109/JSSC.1980.1051512

M. Waltari and K. Halonen, A 10-bit 220-MSample/s CMOS sample-and-hold circuit, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), pp.253-256, 1998.
DOI : 10.1109/ISCAS.1998.704345

T. Choi and R. Brodersen, Considerations for high-frequency switched-capacitor ladder filters, IEEE Transactions on Circuits and Systems, 1980.

S. Lewis, Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.39, issue.8, pp.516-523, 1992.
DOI : 10.1109/82.168943

M. Gustavsson, J. Wikner, and N. Tan, CMOS Data Converters for Communications Integrated Circuits, 2000.

Y. Jenq, Digital spectra of nonuniformly sampled signals: fundamentals and high-speed waveform digitizers, IEEE Transactions on Instrumentation and Measurement, vol.37, issue.2, pp.245-251, 1988.
DOI : 10.1109/19.6060

N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, Explicit analysis of channel mismatch effects in time-interleaved ADC systems, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol.48, issue.3, pp.261-271, 2001.
DOI : 10.1109/81.915383

S. Sin, U. Chio, U. Seng-pan, and R. Martins, Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch, IEEE Transactions Circuit and Systems II, vol.55, issue.7, pp.450-458, 2008.

S. Velasquez, Hybrid Filter Banks for Analog/Digital Conversion, 19997.

C. Lelandais-perrault, T. Petrescu, D. Poulton, P. Duhamel, and J. Oksma, Wideband, Bandpass, and Versatile Hybrid Filter, IEEE Transactions on Circuits and Systems I, issue.8, pp.561772-1782, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00424380

A. Rusu, B. Jose, and H. Tenhunen, A dual-band sigma-delta modulator for gsm/wcdma receivers, DCIS, 2004.

R. Schoofs, M. Steyaert, and W. Sansen, A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.54, issue.1, pp.209-217, 2007.
DOI : 10.1109/TCSI.2006.887455

G. Vemulapalli, P. Hanumolu, Y. J. Kook-andu, and . Moon, A 0.8-V accurately tuned linear continuous-time filter, IEEE Journal of Solid-State Circuits, vol.40, issue.9, pp.401972-1977, 2005.
DOI : 10.1109/JSSC.2005.848170

K. Philips, P. Niujten, R. Roovers, F. Munoz, M. Tejero et al., A 2 mW 89 dB DR Continuous-Time Delta Sigma ADC with Increased Immunity to Wide-band Interferers, IEEE International Solid-State Circuits Conference, 2003.

B. Del-signore, D. A. Kerth, N. S. Sooch, and E. J. , Swanson A Monolithic 20-b Delta- Sigma A/D converter. International Solid-State Circuits Conference, pp.1311-1317, 1990.

K. Nguyen, R. Adams, K. Sweetland, and H. Chen, A 106-DB SNR Hybrid Oversampling Analog-to-Digital Converter for Digital Audio. International Solid-State Circuits Conference, pp.402408-2415, 2005.

L. Quiquerez, A. Kaiser, and D. Billet, A 112 dB Sigma-Delta Converter with a Mixed Continuous-Time/Sampled-Data Architecture Band, Southwest Symposium Journal of Semiconductor Technology and Science, pp.52-57, 1999.

M. Y. Choi, S. N. Lee, S. B. You, W. S. Yeum, H. J. Park et al., Lee A 101-dB SNR Hybrid Delta-Sigma Audio ADC using Post Integration Time Control, IEEE Custom Intergrated Circuits Conference, pp.89-92, 2008.

Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D converters, 2002.

T. Hayashi, Y. Inabe, K. Uchimura, and T. Kimura, A multistage Delta Sigma Modulator Without Double Integration Loop. International Solid-State Circuits Conference, pp.182-183, 1986.

K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata, Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.36, issue.12, pp.1899-1905, 1988.
DOI : 10.1109/29.9034

G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue et al., A 20- mW 640-MHz CMOS Continuous-Time Delta sigma ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB, IEEE Journal of Solid State Circuits, issue.12, pp.412641-2649, 2006.

P. Benabes, M. Keramat, and R. Kielbasa, A methodology for designing continuous-time sigma-delta modulators, Proceedings European Design and Test Conference. ED & TC 97, pp.46-50, 1997.
DOI : 10.1109/EDTC.1997.582328

K. Francken, M. Vogels, E. Martens, and G. Gielen, A Behavioral Simulation Tool for Continuous-Time Delta Sigma Modulators, International Conference on Computer- Aided Design, pp.1234-237, 2002.

R. Schreier and B. Zhang, Delta-sigma modulators employing continuous-time circuitry, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol.43, issue.4, pp.324-332, 1996.
DOI : 10.1109/81.488811

J. Cherry and W. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion, 1999.

Y. , L. Guillou, and H. Fakhoury, Elliptic Filtering in Continuous Time Sigma Delta Converter. Electronic letters, 2005.

O. Shoaei, Continuous-Time Delta-Sigma A/D Converters for High Speed Applications, 1995.

J. Cherry and W. Snelgrove, Excess loop delay in continuous-time delta-sigma modulators, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.46, issue.4, pp.376-389, 1999.
DOI : 10.1109/82.755409

J. Jensen, G. Raghavan, A. Cosand, and R. Walden, A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology, IEEE Journal of Solid-State Circuits, vol.30, issue.10, pp.1119-1127, 1995.
DOI : 10.1109/4.466070
URL : https://hal.archives-ouvertes.fr/hal-00916220

L. Breems, R. Rutten, and G. Wetzker, A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth, IEEE Journal of Solid-State Circuits, vol.39, issue.12, pp.2152-2160, 2004.
DOI : 10.1109/JSSC.2004.836245

T. Salo, Bandpass Delta-Sigma Modulators for Radio Receivers, 2003.

A. Tabatabaei and B. Wooley, A wideband bandpass sigma-delta modulator for wireless applications, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326), pp.91-92, 1999.
DOI : 10.1109/VLSIC.1999.797246

A. Ong and B. Wooley, A two-path bandpass ???? modulator for digital IF extraction at 20 MHz, IEEE Journal of Solid-State Circuits, vol.32, issue.12, pp.1920-1934, 1997.
DOI : 10.1109/4.643650

I. O. Connell and C. Lyden, A High Pass Switched Capacitor ?? Modulator, International Conference on Electronics, Circuits and Systems, pp.307-310, 2002.

H. Khushk, High-Pass ?? Modulator and its Application in Multi-Standard RF Receivers, 2009.
URL : https://hal.archives-ouvertes.fr/pastel-00006055

H. Zare-hoseini, I. Kale, and O. Shoaei, Modeling of Switched-Capacitor Delta???Sigma Modulators in SIMULINK, IEEE Transactions on Instrumentation and Measurement, vol.54, issue.4, pp.1646-1654, 2005.
DOI : 10.1109/TIM.2005.851085

P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato et al., Behavioral modeling of switched-capacitor sigma-delta modulators, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol.50, issue.3, pp.352-364, 2003.
DOI : 10.1109/TCSI.2003.808892

F. Medeiro, B. Perez-verdu, A. Rodriguez-vazquez, and J. Huertas, Modeling Opampinduced Harmonic Distortion for Switched-Capacitor ?? Modulator Design, IEEE International Symposium on Circuits and Systems, pp.445-448, 1994.

B. Razavi, Design of analog CMOS integrated circuits, 2000.

Y. Dong and A. Opal, Time-domain thermal noise simulation of switched capacitor circuits and delta-sigma modulators, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.4, pp.473-481, 2000.
DOI : 10.1109/43.838996

J. Kasdin, Discrete simulation of colored noise and stochastic processes and 1/f/sup ??/ power law noise generation, The Proceedings of the IEEE, pp.802-827, 1995.
DOI : 10.1109/5.381848

P. Cusinato, M. Bruccoleri, D. Caviglia, and M. Valle, Analysis of the behavior of a dynamic latch comparator, IEEE International Symposium on Circuits and Systems, pp.294-297, 1998.
DOI : 10.1109/81.662703

B. Boser and B. Wooley, The design of sigma-delta modulation analog-to-digital converters, IEEE Journal of Solid-State Circuits, vol.23, issue.6, pp.1298-1308, 1988.
DOI : 10.1109/4.90025

P. Vaidyanathan, Multi-rate systems and filter banks. Englewood cliffs, 1993.

R. Khoini-poorfard, L. Lim, and D. Johns, Time-interleaved oversampling A/D converters: theory and practice, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.44, issue.8, pp.44634-645, 1997.
DOI : 10.1109/82.618037

M. Kozak and I. Kale, Novel topologies for time-interleaved delta-sigma modulators, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.47, issue.7, pp.639-654, 2000.
DOI : 10.1109/82.850423

I. Galton and H. T. Jensen, Oversampling parallel delta-sigma modulator A/D conversion, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.43, issue.12, pp.801-810, 1996.
DOI : 10.1109/82.553396

A. Eshraghi and T. Fiez, A Comparative Analysis of Parallel Delta???Sigma ADC Architectures, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, issue.3, pp.450-458, 2004.
DOI : 10.1109/TCSI.2004.823663

P. Aziz, H. Sorensen, and J. Van, Multiband sigma-delta analog to digital conversion, ICASSP, vol.3, pp.249-252, 1994.

P. Benabes, A. Beydoun, and J. Oksman, Extended Frequency-Band Decomposition Sigma Delta A/D. Springer analog integrated circuit and signal processing, pp.75-85, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00411141

A. Eshraghi, High-Speed Parallel Delta-Sigma Analog-To-Digital Converters, 1999.

V. T. Nguyen, P. Loumeau, and J. F. Naviner, Analysis of Time-Interleaved Delta-Sigma Analog to Digital Converter, IEEE Vehicular Technology Conference, vol.4, pp.1594-1597, 2002.

V. T. Nguyen, P. Loumeau, and J. F. Naviner, An interleaved delta-sigma analog to digital converter with digital correction, IIEEE International Conference on Acoustics Speech and Signal Processing, 2002.
DOI : 10.1109/ICASSP.2002.1004941

F. Chen and C. Huang, Analytical Settling Noise Models of Single-Loop Sigma–Delta ADCs, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.56, issue.10, pp.753-757, 2009.
DOI : 10.1109/TCSII.2009.2027949

J. Ma, Y. Ye, Z. Li, and M. Yu, Compact Channel Noise Models for Deep-Submicron Mosfets, IEEE Transactions on Electron Devices, vol.56, issue.6, pp.1300-1308, 2009.

K. Poulton, J. J. Corcoran, and T. Hornak, A 1-GHz 6-bit ADC system, IEEE Journal of Solid-State Circuits, vol.22, issue.6, pp.22962-970, 1987.
DOI : 10.1109/JSSC.1987.1052844

M. Waltari and K. Halonen, Timing skew insensitive switching for double sampled circuits, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999.
DOI : 10.1109/ISCAS.1999.780619

D. Camarero, K. Ben-kalaia, J. F. Naviner, and P. Loumeau, Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, issue.11, pp.553676-3687, 2008.
DOI : 10.1109/TCSI.2008.926314

H. Jin and E. Lee, A Digital-Background Calibration Technique for Minimizing Timing- Error Effects in Time-Interleaved ADCs, IEEE Transactions on Circuits and Systems, vol.II, issue.7, pp.47603-613, 2000.

L. Wu and W. C. Jr, A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator for Time-Interleaved Applications, IEEE International Solid-State Circuits Conference, pp.396-397, 2001.

V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati, and F. Maloberti, Gain and Offset Mismatch Calibration in Time-Interleaved Multipath A/D Sigma???Delta Modulators, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, issue.12, pp.512365-2373, 2004.
DOI : 10.1109/TCSI.2004.838154

R. Batten, A. Eshraghi, and T. Fiez, Calibration of parallel ???? ADCs, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.49, issue.6, pp.390-399, 2002.
DOI : 10.1109/TCSII.2002.803468

A. Beydoun, V. T. Nguyen, and P. Loumeau, A Novel Digital Calibration Technique for Gain and Offset Mismatch in Parallel TI Delta Sigma ADCs, IEEE, 2010.

A. Shoval, D. Johns, and W. Snelgrove, Comparison of DC offset effects in four LMS adaptive algorithms, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.42, issue.3, pp.176-185, 1995.
DOI : 10.1109/82.372867

J. Silva, U. Moon, and G. Temes, Wideband low-distortion delta-sigma ADC topology, Electronics Letters, vol.37, issue.12, pp.737-738, 2001.
DOI : 10.1049/el:20010542

G. Cauwenberghsand and G. Temes, Aadaptive Digital Correction of Analog Errors in Mash ADCs part I: Off-line and blind on-line calibration, IEEE Transactions on Circuits and Systems II, issue.7, pp.47621-628, 2000.

P. Kiss, J. Silva, A. Wiesbauer, T. Sun, U. K. Moon et al., adaptive Digital Correction of Analog Errors in Mash ADCs part II: Correction using test-signal injection, IEEE Transactions on Circuits and Systems II, issue.7, pp.47629-638, 2000.

V. T. Nguyen, P. Loumeau, and H. Fakhoury, Convertisseur Sigma-Delta, pp.8-58632, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00920972

V. T. Nguyen, P. Loumeau, and P. Benabes, Convertisseur Sigma-Delta. European Patent, pp.8-53213, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00920972

M. Maghami and M. Yavari, A Double-Sampled Hybrid CT/DT Smash Delta Sigma Modulator for Wideband applications, IEEE International Conference on Electronics, Circuits, and Systems, pp.41-44, 2009.

A. Abo, Design for Reliability of Low-voltage, Switched-capacitor Circuits, 1999.

D. Groeneveld, H. Schouwenaars, H. Termeer, and C. Bastiaansen, A Self-Calibration Technique for Monolithic High-Resolution D/A Converters, IEEE Journal of Solid State Circuits, issue.6, p.24, 1989.

R. Baird and T. Fiez, Linearity enhancement of multibit ???? A/D and D/A converters using data weighted averaging, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.42, issue.12, pp.42753-762, 1995.
DOI : 10.1109/82.476173

Y. Liu, K. Yi, and G. Gielen, Interleaved data weighted averaging technique for speed/power relaxation in multi-bit DACs, Electronics Letters, vol.46, issue.1, 2010.
DOI : 10.1049/el.2010.2645

N. Maghari, G. C. Temes, and U. Moon, Single-loop Delta Sigma Modulator with Extended Dynamic Range, Electronic Letters, issue.25, p.44, 2008.

R. Van-veldhoven, R. Rutten, and L. Breems, An Inverter-Based Hybrid Sigma Delta Modulator, IEEE International Solid-State Circuits Conference, pp.492-494, 2003.

L. Bos, G. Vandersteen, J. Ryckaert, P. Rombouts, Y. Rolain et al., Multirate 3.4-to-6.8mW 85-to-66dB DR GSM, UMTS Cascade DT in 90nm Digital CMOS. IEEE International Solid-State Circuits Conference ISSCC, 2009.

T. Christen, T. Burger, and Q. Huang, A 0.13um CMOS EDGE/UMTS/WLAN Tri- Mode Delta Sigma ADC with -92dB THD. IEEE International Solid-State Circuits Conference, 2007.

J. Järvinen and K. Halonen, A 1.2V Dual-Mode GSM/WCDMA Delta Sigma Modulator in 65nm CMOS, IEEE International Solid-State Circuits Conference, 2006.

A. Dezzani and E. Andre, A 1.2-V Dual-Mode WCDMA/GPRS Sigma-Delta Modulator, IEEE International Solid-State Circuits Conference, 2003.

A. Gharbiya and D. Johns, A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator, IEEE Journal of Solid-State Circuits, vol.44, issue.7, pp.2010-2018, 2009.
DOI : 10.1109/JSSC.2009.2021916

Y. Fujimoto, Y. Kanazawa, P. Lo-ré, and K. Iizuka, A 100 MS/s 4 MHz Bandwidth 70 dB SNR <formula formulatype="inline"><tex Notation="TeX">$\Delta \Sigma$</tex></formula> ADC in 90 nm CMOS, IEEE Journal of Solid-State Circuits, vol.44, issue.6, pp.1697-1708, 2009.
DOI : 10.1109/JSSC.2009.2020458

J. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka et al., A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, 98 dB THD, and 79 dB SNDR, IEEE Journal of Solid State Circuits, issue.12, pp.432601-2612, 2008.

J. Paramesh, R. Bishop, K. Soumyanath, and D. Allstot, An 11-bit 330 Mhz 8x OSR Sigma Delta Modulator for Next-Generation WLAN. Symposium on VLSI Circuits Digest of Technical Papers, 2006.

P. Balmelli and Q. Huang, A 25-MS/s 14-b 200-mW /spl Sigma//spl Delta/ Modulator in 0.18-/spl mu/m CMOS, IEEE Journal of Solid-State Circuits, vol.39, issue.12, pp.2161-2169, 2004.
DOI : 10.1109/JSSC.2004.836240

D. Johns and K. Martin, Analog integrated cirsuit design, 1997.

P. , M. Ferreira, H. Petit, and J. F. Naviner, Ams and RF Design for Reliability Methodology, IEEE International Symposium on Circuits and Systems, 2010.

G. Gielen, P. De-wit, E. Maricau, J. Loeckxl, J. Martin-martinez et al., Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies, IEEE Design, Automation and Test in Europe, pp.1322-1327, 2008.

J. Cohn, D. Garrod, and R. Rutenbar, Analog Device-Level Layout Automation, 1994.
DOI : 10.1007/978-1-4615-2756-5

M. Dessouky and A. Kaiser, Very low-voltage digital-audio ???? modulator with 88-dB dynamic range using local switch bootstrapping, IEEE Journal of Solid-State Circuits, vol.36, issue.3, pp.349-355, 2001.
DOI : 10.1109/4.910473
URL : https://hal.archives-ouvertes.fr/hal-01197325

D. Aksin, M. Shyoukh, and F. Maloberti, A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005., pp.743-746, 2005.
DOI : 10.1109/CICC.2005.1568775

L. Wang, J. Ren, W. Yin, T. Chen, and J. Xu, AA High-Speed High-Resolution Low- Distortion CMOS Bootstrapped Switch, IEEE International Symposium on Circuits and Systems, pp.1721-1724, 2007.

A. Abo and P. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE Journal of Solid-State Circuits, vol.34, issue.5, pp.599-606, 1999.
DOI : 10.1109/4.760369
URL : https://hal.archives-ouvertes.fr/inserm-00172159

O. Adeniran and A. Demosthenous, Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range Delta Sigma Modulators, IEEE Transactions on Circuits and Systems I, issue.10, pp.553324-3345, 2008.

J. Yuan, N. Farhat, and J. Van, Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, issue.1, pp.311-321, 2008.
DOI : 10.1109/TCSI.2007.910645

S. Lee, Y. Kim, H. Cho, and G. Ahn, A 1.2-V 12-b 120-ms/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode calibration, IEEE Transactions on Circuits and Systems I, vol.56, issue.5, pp.894-901, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00995626

K. Lee, M. Miller, and G. C. Temes, An 8.1 mW, 82 dB Delta-Sigma ADC with 1.9 MHz BW and -98 dB THD, IEEE Journal of Solid-State Circuits, issue.8, pp.442202-2211, 2009.

D. Haigh and B. Singh, A Switching Scheme for Switched Capacitor Filters which Reduces the Effect of Parasitic Capacitances Associated with Switch Control Terminals, IEEE International Symposium on Circuits and Systems, pp.586-589, 1983.

M. Waltari, Circuit Techniques for Low-Voltage and High-Speed A/D Converters, 2002.

J. Wu and B. Wooley, A 100 MHz Pipelined CMOS Comparator, IEEE Journal of Solid-State Circuits, vol.23, issue.6, pp.1379-1385, 1988.

G. M. Yin, F. Op-'t-eynde, and W. Sansen, A high-speed CMOS comparator with 8-b resolution, IEEE Journal of Solid-State Circuits, vol.27, issue.2, pp.208-211, 1992.
DOI : 10.1109/4.127344