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UML-Based Design Space Exploration, Fast Simulation and Static Analysis

Abstract : Design Space Exploration at system level is carried out early in the design flow of embedded systems and Systems-on-Chip. The objective is to identify a suitable hardware/software partitioning that complies to a given set of constraints regarding functionality, performance, silicon area, power consumption, etc. In early design stages, accurate system models, such as RTL models, may not yet be available. Moreover, the complexity of these models comes with the downside of being demanding and slow in verification. It is commonly agreed that the only remedy to that problem is abstraction, which triggered the advent of virtual platforms based on techniques like Transaction Level Modeling. Non-functional, \textit{approximately timed} models go even further by abstracting data to its mere presence or absence and introducing symbolic instructions. The DIPLODOCUS methodology and its related UML profile realize the aforementioned abstractions. It relies on the y-Chart approach, that treats functionality (called application) and its implementation (called architecture) in an orthogonal way. DIPLODOCUS' formal semantics paves the way for both simulation and formal verification, which has been shown prior to this work. This thesis proposes enhancements to the methodology that make it amenable to verification of functional and non-functional properties. At first, we focus on the way functional properties are expressed. As verification of high level models is usually conducted with temporal logic, we suggest a more intuitive way, matching the abstraction level of the model to be verified. The graphical but formal language TEPE is the first contribution of this work. To achieve a high level of confidence in verification in a reasonable amount of time, the model needs to be executed in an efficient way. The second contribution consists of an execution semantics for DIPLODOCUS and a simulation strategy that leverages abstractions. The benefit is that a coarse granularity of the application model directly translates into an increase in simulation speed. As a third contribution, we present a trade-off between the limited coverage of simulation and the exhaustiveness of formal techniques. Especially for large models, the latter may be hampered by the state explosion problem. As a result of data abstraction, DIPLODOCUS application models embrace non-deterministic operators. Coverage-enhanced simulation aims at exploiting a subset or all valuations of the corresponding random variables. Therefore, the DIPLODOCUS model is statically analyzed and information characterizing the significant state space of the application is propagated to the simulator. Finally, we provide evidence for the applicability of contributions by means of a case study in the signal processing domain. It will be shown that common system properties easily translate into TEPE. Moreover fast simulation and coverage-enhanced simulation provide valuable insights that may assist the designer in configuring a Software Defined Radio platform.
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Contributor : Daniel Knorreck <>
Submitted on : Wednesday, January 25, 2012 - 9:15:09 AM
Last modification on : Monday, October 19, 2020 - 11:04:14 AM
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  • HAL Id : pastel-00662744, version 1


Daniel Knorreck. UML-Based Design Space Exploration, Fast Simulation and Static Analysis. Electronics. Télécom ParisTech, 2011. English. ⟨pastel-00662744⟩



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