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Méthodes probabilistes d'analyse de fiabilité dans la logique combinatoire

Abstract : Digital circuits used in such domains as automotive, medical, space or nuclear need to satisfy high reliability requirements. In addition, continous downscaling of consumer electronics consisting in increased integration and lower voltage supply, affects system's sensitivity to several phenomena involved in transient and permament faults generation: particle strike, thermal noise, crosstalk, etc. Transient faults in memories and sequential elements have largely dominated the overall soft error rate (SER) of systems, thus, correction and prevention techniques for these devices are well known, and their application is widely spread. Though, it is expected that the contribution of combinational logic elements to the system's SER becomes dominant with CMOS technology downscaling. Hence, there is a need to fulfill the lack of avalaible models and methodologies that take into account the combinational logic's contribution to the reliability loss. Two main approaches exist to assess this issue: 1. Fault Injection tehcniques 2. Analytical models The work presented here is focused on the analytical approach, also knon as probabilistic approach. First, an in-depth analysis of the state of the art is done pointing out the main limitations of probabilistic models. Second, innovative heuristics and approaches are proposed, improving the performance of the state of the art methods. Then, new metrics addressing the slective hardening problem and FMDEA analysis are investigated. Finally, we validate our approaches by comparing the performances of our methods with alternative techniques.
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Contributor : Josep Torras Flaquer <>
Submitted on : Monday, March 12, 2012 - 1:05:39 PM
Last modification on : Monday, August 3, 2020 - 5:20:03 PM
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  • HAL Id : pastel-00678275, version 1

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Josep Torras Flaquer. Méthodes probabilistes d'analyse de fiabilité dans la logique combinatoire. Electronique. Télécom ParisTech, 2011. Français. ⟨pastel-00678275⟩

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