. Afin-de-tester-la-tolérance-aux-fautes-sur-le-cycab, Pour cela nous avons codé l'opération "SpeedControl", initialement codée pour le mictrocontrôleur MPC555, pour le dsPICs Nous avons ajouté des opérations de conversions de données "conv1", "conv2" et "conv3", comme le montre la figure 8.13, car les MPC555 et les dsPICs n'utilisent pas le même codage de données. Les opérations "TI" et "conv1" sont allouées à l'opérateur "root", l'opérations "SpeedControl" est allouée à l'opérateur "dspic1" et le reste des opérations sont allouées aux opérateurs "f555" et "r555". La durée d'exécution du traitement d'images varie entre 70ms et 100ms alors que celle de l'opération de conversion "conv1" est négligeable devant le traitement d'images. La somme de ces deux durées d'exécutions est du même ordre que celle du traitement d'images. Afin que ces deux opérations puissent être ordonnancées sur le même opérateur "root" ils faut qu'elles satisfassent la condition, Comme C 1 + C 2 ? C 1 ? 100ms et P GCD(T 1 , T 2 ) = 200ms alors la condition (3.12) est satisfaite et ces deux opérations sont ordonnançables sur le même processeur. Le reste des opérations de contrôle ont toutes une période de 10ms et sont ordonnancées sur le reste des processeurs

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