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ASIC Design Methodology for 3D NOC Based Heterogeneous Multi Processor on Chip

Abstract : ITRS Road Map predicts that the number of cores in the same chip will increase following an exponential curve. Insuring the interconnections between the different cores in the same chip is a real challenge when the number of components is high. The use of the NoC (Network On Chip) is a suitable solution overcoming the limitations of the classical interconnects methodologies. The regular NoC topology is costly in term of area and power consumption that is why designing an optimized architecture is a major problematic in MPSOC design. Moreover, with the semi-conductor CMOS shrinking, the interconnect delay has overcome the gate delay. In fact there is a real need to find other methodologies to continue the evolution of the chip design. 3D IC is one of the promising solutions which can reduce the interconnect delay, minimize the area of the chip and allow the use of mixed technologies. With the shortage of real 3D IC MPSOC implementation, we propose in this thesis to study the 3D design methodologies on ASIC for MPSOC architectures based on 3D NoC. Even though the NoC was proven to be an efficient solution to deal with the interconnect problems between the different cores, only few works have validated the architectures based NoC by a real implementation on FPGA/ASIC. We consider that the validation of 3D NoC by synthesis, place and route workflow is an essential step which guarantees the good functionality of the architecture before moving to 3D technology. That is why we have validated our MPSOC based 16 PEs architecture with a butterfly NoC on different FPGAs platforms. 3D IC design is facing new challenges like TSV assignment, heat dissipation and partitioning problems. That is why, in order to generate an optimized 3D NoC for a specific application and subject to the 3D Tezzaron technology, we propose in this work a new 3D NoC synthesis methodology based on MOEA. A real 3D IC design implementation of our tested and validated 3D MPSOC architecture was performed using the 3D IC Tezzaron technique. Our real case study represents a significant example proving that there is no actual 3D tool taking in consideration all the 3D IC challenges like mapping and partitioning.
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Contributor : Abir M'Zah Connect in order to contact the contributor
Submitted on : Tuesday, January 1, 2013 - 8:48:54 PM
Last modification on : Wednesday, May 11, 2022 - 3:20:03 PM
Long-term archiving on: : Tuesday, April 2, 2013 - 3:49:00 AM


  • HAL Id : pastel-00769455, version 1



Abir M'Zah. ASIC Design Methodology for 3D NOC Based Heterogeneous Multi Processor on Chip. Micro and nanotechnologies/Microelectronics. Ecole Polytechnique X, 2012. English. ⟨pastel-00769455⟩



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