S. Guilley, S. Chaudhuri, L. Sauvage, and T. Graba, Jean- Luc Danger, Philippe Hoogvorst, Vinh-Nga Vong, Maxime Nassar Placeand-Route Impact on the Security of DPL Designs in FPGAs, 2008.

S. Bhasin, J. Danger, F. Flament, T. Graba, S. Guilley et al., Maxime Nassar, Laurent Sauvage and Nidhal Selmane. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow, ReConFig, pp.213-218, 2009.

M. Nassar, S. Bhasin, J. Danger, G. Duc, and S. Guilley, BCDL: A high performance balanced DPL with global pre? charge and without early-evaluation, DATE 10, pp.849-854, 2010.

Y. Souissi, M. Nassar, and S. Guilley, Jean-Luc Danger et Flament Florent First Principal Components Analysis: A New Side Channel Distinguisher, ICISC 2010 LNCS 14th Annual International Conference on Information Security and Cryptology

Y. Souissi and J. , Danger and Sami Mekki and Sylvain Guilley and Maxime Nassar Techniques for electromagnetic attacks enhancement, DTIS (Design & Technologies of Integrated Systems) 2010

Y. Souissi, M. Nassar, S. Guilley, S. Bhasin, and J. Danger, Embedded systems security: An evaluation methodology against Side Channel Attacks, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011.
DOI : 10.1109/DASIP.2011.6136885

N. Debande, Y. Souissi, S. Guilley, J. Danger, M. Nassar et al., “Re-synchronization by moments”: An efficient solution to align Side-Channel traces, 2011 IEEE International Workshop on Information Forensics and Security
DOI : 10.1109/WIFS.2011.6123143

M. Nassar, Y. Souissi, S. Guilley, and J. Danger, ???Rank Correction???: A New Side-Channel Approach for Secret Key Recovery, Info Sec HiComNet 2011 International Conference
DOI : 10.1007/978-3-642-01001-9_26

Y. Souissi, S. Guilley, M. Nassar, S. Bhasin, and J. Danger, Time-Success rate " as a new security metric for Side-Channel Analysis, Poster Session of CHES 2011

Y. Souissi, S. Bhasin, M. Nassar, S. Guilley, and J. Danger, Combination of Measurements to accelerate side channel attacks, Poster Session of CHES, 2011.

S. Guilley, G. Duc, . Ph, M. Hoogvorst, S. Aziz-elaabid et al., Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
DOI : 10.1109/DTIS.2011.5941419

URL : https://hal.archives-ouvertes.fr/hal-00579020

[. Debande, Y. Souissi, M. Nassar, S. Guilley, T. Le et al., Side Channel Analysis enhancement: A proposition for measurements resynchronisation, 2011.

M. Nassar, S. Guilley, and J. , Danger Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks, INDOCRYPT 2011, pp.22-39

Y. Souissi, S. Bhasin, M. Nassar, S. Guilley, J. Danger et al., Towards Different Flavors of Combined Side Channel Attacks, RSA Cryptographers Track, 2012.
DOI : 10.1007/978-3-642-00730-9_16

M. Nassar, S. Guilley, and J. , Danger and Youssef Souissi RSM: a Small and Fast Countermeasure for AES, Secure against First-and Second-order Zero-Offset SCAs, DATE 2012

M. Abdelaziz, E. Aabid, S. Guilley, and P. Hoogvorst, Template Attacks with a Power Model, Cryptology ePrint Archive Report, vol.443443, issue.9, 2007.

M. Abdelaziz, E. Aabid, O. Meynard, S. Guilley, and J. Danger, Combined Side-Channel Attacks, WISA, pp.175-190

. Springer, Jeju Island, Korea. DOI: 10, 2010.

T. Akishita and T. Takagi, Zero-Value Point Attacks on Elliptic Curve Cryptosystem, Proc. Information Security -ISC, pp.218233-218247, 2003.
DOI : 10.1007/10958513_17

M. Akkar, R. Bevan, and L. Goubin, Two Power Analysis Attacks against One-Mask Methods, Fast Software Encryption, 11th International Workshop, pp.332-347, 2004.
DOI : 10.1007/978-3-540-25937-4_21

URL : https://hal.archives-ouvertes.fr/hal-00153177

M. Akkar and C. Giraud, An Implementation of DES and AES, Secure against Some Attacks, Proceedings of CHES'01, pp.309-318, 2001.
DOI : 10.1007/3-540-44709-1_26

M. Akkar and L. Goubin, A Generic Protection against High-Order Differential Power Analysis, Proceedings of FSE'03, pp.192-205, 2003.
DOI : 10.1007/978-3-540-39887-5_15

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.641.9911

P. Alain, F. , and F. Valette, The doubling attack why upwards is better than, Downwards, Workshop on Cryptographic Hardware and Embedded Systems 2003 (CHES 2003), pp.269-280, 2003.

C. Archambeau, É. Peeters, F. Standaert, and J. Quisquater, Template Attacks in Principal Subspaces, CHES, pp.1-14, 2006.
DOI : 10.1007/11894063_1

B. C. Arnold, E. Castillo, and J. M. Sarabia, Conditional specification of statistical models. Springer series in statistics, p.143, 1999.

S. Aumonier, Generalized Correlation Power Analysis, ECRYPT Workshop " Tools for Cryptanalysis, pp.24-25, 0137.

K. Baddam and M. Zwolinski, Divided Backend Duplication Methodology for Balanced Dual Rail Routing, CHES, pp.396-410, 2008.
DOI : 10.1007/978-3-540-85053-3_25

B. Badrignans, J. Danger, V. Fischer, G. Gogniat, and L. Torres, Security Trends for FPGAS ? From Secured to Secure Reconfigurable Systems, 2011.

H. Bar-el, H. Choukri, D. Naccache, M. Tunstall, and C. Whelan, The Sorcerer's Apprentice Guide to Fault Attacks, Proceedings of the IEEE, vol.94, issue.2, pp.370-382, 2006.
DOI : 10.1109/JPROC.2005.862424

L. Batina, B. Gierlichs, and K. Lemke-rust, Comparative Evaluation of Rank Correlation Based DPA on an AES Prototype Chip, ISC, pp.341-354, 2008.
DOI : 10.1007/978-3-540-85886-7_24

L. Batina, B. Gierlichs, E. Prouff, M. Rivain, F. Standaert et al., Mutual Information Analysis: a??Comprehensive Study, Journal of Cryptology, vol.4, issue.3, pp.269-291, 2011.
DOI : 10.1007/s00145-010-9084-8

G. Bertoni, L. Breveglieri, I. Koren, and P. Maistri, An efficient hardware-based fault diagnosis scheme for AES: performances and cost, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings., pp.130-138, 2004.
DOI : 10.1109/DFTVS.2004.1347833

G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, and V. Piuri, Error analysis and detection procedures for a hardware implementation of the advanced encryption standard, IEEE Transactions on Computers, vol.52, issue.4, pp.492-505, 2003.
DOI : 10.1109/TC.2003.1190590

R. Bevan and E. Knudsen, Ways to Enhance Differential Power Analysis, ICISC, pp.327-342, 2002.
DOI : 10.1007/3-540-36552-4_23

S. Bhasin, J. Danger, F. Flament, T. Graba, S. Guilley et al., Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow, 2009 International Conference on Reconfigurable Computing and FPGAs, pp.213-218, 2009.
DOI : 10.1109/ReConFig.2009.50

URL : https://hal.archives-ouvertes.fr/hal-00411843

S. Bhasin, J. Danger, T. Graba, and S. Guilley, How to design BCDL Logic with the best Trade-off between Complexity and Robustness, p.89, 2011.

S. Bhasin, S. Guilley, Y. Souissi, and J. Danger, Efficient FPGA Implementation of dual-rail countermeasures using Stochastic Models, Non-Invasive Attack Testing Workshop, 2011.

I. Biehl, B. Meyer, and V. Müller, Differential Fault Attacks on Elliptic Curve Cryptosystems, CRYPTO '00: Proceedings of the 20th Annual International Cryptology Conference on Advances in Cryptology, pp.131-146, 2000.
DOI : 10.1007/3-540-44598-6_8

I. Biehl, B. Meyer, and V. Müller, Differential Fault Attacks on Elliptic Curve Cryptosystems, Lecture Notes in Computer Science, vol.1880, pp.131-146, 2000.
DOI : 10.1007/3-540-44598-6_8

E. Biham and A. Shamir, Differential fault analysis of secret key cryptosystems, CRYPTO, pp.513-525, 1997.
DOI : 10.1007/BFb0052259

J. Blömer, J. Guajardo, and V. Krummel, Provably Secure Masking of AES, Proceedings of SAC'04, pp.69-83, 2004.
DOI : 10.1007/978-3-540-30564-4_5

J. Blömer and J. Seifert, Fault Based Cryptanalysis of the Advanced Encryption Standard (AES), Financial Cryptography, pp.162-181, 2003.
DOI : 10.1007/978-3-540-45126-6_12

D. Boneh, R. A. Demillo, and R. J. Lipton, On the Importance of Checking Cryptographic Protocols for Faults, Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques, EUROCRYPT'97, pp.37-51, 1997.
DOI : 10.1007/3-540-69053-0_4

A. Boscher, H. Handschuh, and E. Trichina, Blinded fault resistant exponentiation revisited. Fault Diagnosis and Tolerance in Cryptography, pp.3-9, 2009.

E. Brier and M. Joye, Weierstra?? Elliptic Curves and Side-Channel Attacks, Public Key Cryptography, vol.2274, pp.335-369, 2002.
DOI : 10.1007/3-540-45664-3_24

É. Brier, C. Clavier, and F. Olivier, Correlation Power Analysis with a Leakage Model, CHES, pp.16-29
DOI : 10.1007/978-3-540-28632-5_2

M. Bär, H. Drexler, and J. Pulkus, Improved Template At- tacks, In COSADE, pp.81-89, 2010.

D. Canright and L. Batina, A very compact "perfectly masked" s-box for aes 21 BIBLIOGRAPHY [36] Claude Carlet. Boolean Functions for Cryptography and Error Correcting Codes: Chapter of the monography Boolean Models and Methods in Mathematics, Proceedings of the 6th international conference on Applied cryptography and network security, ACNS'08 Preliminary version available at, pp.446-459, 2008.

S. Chari, C. S. Jutla, J. R. Rao, and P. Rohatgi, Towards Sound Approaches to Counteract Power-Analysis Attacks, CRYPTO, volume 1666 of LNCS, 1999.
DOI : 10.1007/3-540-48405-1_26

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.94.8951

S. Chari, J. R. Rao, and P. Rohatgi, Template Attacks, CHES, pp.13-28, 2002.
DOI : 10.1007/3-540-36400-5_3

Z. Chen and Y. Zhou, Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage, CHES, pp.242-254, 2006.
DOI : 10.1007/11894063_20

M. Benoit-chevallier-mames, M. Ciet, and . Joye, Low-cost solutions for preventing simple side-channel analysis: side-channel atomicity, IEEE Transactions on Computers, vol.53, issue.6, p.33, 2003.
DOI : 10.1109/TC.2004.13

M. Ciet, Aspects of Fast and Secure Arithmetics for Elliptic Curve Cryptography, p.39, 2003.

M. Ciet and M. Joye, (Virtually) Free Randomization Techniques for Elliptic Curve Cryptography, Information and Communications Security, p.39, 2003.
DOI : 10.1007/978-3-540-39927-8_32

M. Ciet and M. Joye, Elliptic Curve Cryptosystems in the Presence of Permanent and Transient Faults, Designs, Codes and Cryptography, vol.13, issue.4, pp.33-43, 2005.
DOI : 10.1007/s10623-003-1160-8

C. Clavier and M. Joye, Universal Exponentiation Algorithm A First Step towards Provable SPA-Resistance, Cryptographic Hardware and Embedded Systems -CHES 2001, pp.300-308, 2001.
DOI : 10.1007/3-540-44709-1_25

J. Coron, Resistance Against Differential Power Analysis For Elliptic Curve Cryptosystems, Proceedings of CHES'99, pp.292-302, 1999.
DOI : 10.1007/3-540-48059-5_25

J. Coron, Resistance Against Differential Power Analysis For Elliptic Curve Cryptosystems, Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems, CHES '99, pp.292-302, 1999.
DOI : 10.1007/3-540-48059-5_25

E. Jean-sébastien-coron, M. Prouff, and . Rivain, Side Channel Cryptanalysis of a Higher Order Masking Scheme, CHES, pp.28-44

N. Courtois and L. Goubin, An Algebraic Masking Method to Protect AES Against Power Attacks, Lecture Notes in Computer Science, vol.3935, pp.199-209, 2005.
DOI : 10.1007/11734727_18

URL : https://hal.archives-ouvertes.fr/hal-00153174

P. Dagnelie, Statistique théorique et appliquée Tome 2, Inférence statistique à une et à deux dimensions, p.143, 2006.

N. Debande, Y. Souissi, S. Guilley, J. Danger, and M. Nassar, “Re-synchronization by moments”: An efficient solution to align Side-Channel traces, 2011 IEEE International Workshop on Information Forensics and Security, pp.1-6, 2011.
DOI : 10.1109/WIFS.2011.6123143

J. Dhem, F. Koeune, P. Leroux, P. Mestre, J. Quisquater et al., A Practical Implementation of the Timing Attack, CARDIS, pp.167-182, 1998.
DOI : 10.1007/10721064_15

S. Drimer, Security for Volatile FPGAs (university of Cambrige technical report number 763), 0102.

H. M. Edwards, A Normal Form for Elliptic Curves. Bulletin of the, pp.393422-393456, 2007.

R. Pierre-alain-fouque, D. Lercier, F. Réal, and . Valette, Fault attack on elliptic curve montgomery ladder implementation, FDTC '08: Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography, pp.92-98, 2008.

D. Pierre-alain-fouque, F. Réal, M. Valette, and . Drissi, The carry leakage on the randomized exponent countermeasure, Cryptographic Hardware and Embedded Systems -CHES 2008, 10th International Workshop Proceedings, pp.198-213, 2008.

P. Fouque and F. Valette, The Doubling Attack ??? Why Upwards Is Better than Downwards, pp.269-280, 2003.
DOI : 10.1007/978-3-540-45238-6_22

URL : https://hal.archives-ouvertes.fr/inria-00563965

G. Fumaroli, A. Martinelli, E. Prouff, and M. Rivain, Affine Masking against Higher-Order Side Channel Analysis, Selected Areas in Cryptography, pp.262-280, 2010.
DOI : 10.1007/3-540-45325-3_6

K. Gandolfi, C. Mourtel, and F. Olivier, Electromagnetic Analysis: Concrete Results, CHES, pp.251-261, 2001.
DOI : 10.1007/3-540-44709-1_21

S. Ghosh, M. Alam, D. R. Gupta, and . Chowdhury, A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp.109-115, 2007.
DOI : 10.1109/DSD.2007.4341457

B. Gierlichs, L. Batina, B. Preneel, and I. Verbauwhede, Revisiting Higher-Order DPA Attacks:, LNCS, vol.5985, pp.221-234, 2010.
DOI : 10.1007/978-3-642-11925-5_16

B. Gierlichs, L. Batina, P. Tuyls, and B. Preneel, Mutual Information Analysis, CHES, 10th International Workshop, pp.426-442, 2008.
DOI : 10.1007/978-3-540-85053-3_27

B. Gierlichs, E. D. Mulder, B. Preneel, and I. Verbauwhede, Empirical comparison of side channel analysis distinguishers on DES in hardware, 2009 European Conference on Circuit Theory and Design, pp.391-394, 2009.
DOI : 10.1109/ECCTD.2009.5275003

B. Gierlichs, K. Lemke-rust, and C. Paar, Templates vs. Stochastic Methods, CHES, pp.15-29, 2006.
DOI : 10.1007/11894063_2

J. Dj, C. Golic, and . Tymen, Multiplicative Masking and Power Analysis of AES, CHES, pp.198-212, 2002.

L. Goubin, A Refined Power-Analysis Attack on Elliptic Curve Cryptosystems, Proceedings of the 6th International Workshop on Theory and Practice in Public Key Cryptography: Public Key Cryptography, pp.199-210, 2003.
DOI : 10.1007/3-540-36288-6_15

L. Goubin, A Refined Power-Analysis Attack on Elliptic Curve Cryptosystems, Proceedings of the 6th International Workshop on Theory and Practice in Public Key Cryptography: Public Key Cryptography, PKC '03, pp.199-210, 2003.
DOI : 10.1007/3-540-36288-6_15

L. Goubin and J. Patarin, DES and Differential Power Analysis The ???Duplication??? Method, CHES, LNCS, pp.158-172, 1999.
DOI : 10.1007/3-540-48059-5_15

F. J. Gravetter and L. B. Wallnau, Essentials of statistics for the behavioral sciences, p.144, 2008.

S. Guilley, S. Chaudhuri, L. Sauvage, T. Graba, J. Danger et al., Vinh-Nga Vong, and Maxime Nassar. Place-and-Route Impact on the Security of DPL Designs in FPGAs, HOST, IEEE, pp.29-35, 2008.

S. Guilley, F. Flament, R. Pacalet, P. Hoogvorst, and Y. Mathieu, Security Evaluation of a Balanced Quasi-Delay Insensitive Li- brary

D. In, . Grenoble, and . France, Session 5D ? Reliable and Secure Architectures, ISBN: 978-2-84813-124-5, full text in HAL, p.58, 2008.

S. Guilley, P. Hoogvorst, Y. Mathieu, and R. Pacalet, The ???Backend Duplication??? Method, CHES, pp.383-397, 2005.
DOI : 10.1007/11545262_28

S. Guilley, P. Hoogvorst, and R. Pacalet, A fast pipelined multi-mode DES architecture operating in IP representation, Integration, the VLSI Journal, vol.40, issue.4, pp.479-489, 2007.
DOI : 10.1016/j.vlsi.2006.06.004

S. Guilley, K. Khalfallah, V. Lomne, and J. Danger, Formal Framework for the Evaluation of Waveform Resynchronization Algorithms WISTP: Information Security Theory and Practices. Smart Cards, Mobile and Ubiquitous Computing, LNCS, editor, pp.100-115, 2011.

N. Hanley, R. Mcevoy, M. Tunstall, C. Whelan, C. Murphy et al., Correlation Power Analysis of Large Word Sizes, ISSC (Irish Signals and System Conference), pp.145-150, 2007.

N. Hanley, M. Tunstall, and W. P. Marnane, Unknown Plaintext Template Attacks, WISA, pp.148-162
DOI : 10.1007/978-3-642-10838-9_12

N. Homma, A. Miyamoto, T. Aoki, A. Satoh, and A. Shamir, Comparative Power Analysis of Modular Exponentiation Algorithms, IEEE Transactions on Computers, vol.59, issue.6, pp.795-807, 2010.
DOI : 10.1109/TC.2009.176

P. Hoogvorst, The Variance Power Attack, In COSADE, pp.4-9, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00479595

E. Brier, I. Dechene, and M. Joye, Unified Point Addition Formulae for Elliptic Curve Cryptosystems, Embedded Cryptographic Hardware : Methodologies and Architectures, pp.24725-24759, 2004.

Y. Ishai, A. Sahai, and D. Wagner, Private Circuits: Securing Hardware against Probing Attacks, CRYPTO, volume 2729 of Lecture Notes in Computer Science, pp.463-481, 2003.
DOI : 10.1007/978-3-540-45146-4_27

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.115.9436

K. Itoh, T. Izu, and M. Takenaka, Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA, Cryptographic Hardware and Embedded Systems -CHES 2002, pp.399-412, 2003.
DOI : 10.1007/3-540-36400-5_11

K. Itoh, T. Izu, and M. Takenaka, A Practical Countermeasure against Address-Bit Differential Power Analysis, Cryptographic Hardware and Embedded Systems -CHES 2003, pp.382-396, 2003.
DOI : 10.1007/978-3-540-45238-6_30

T. Izu and T. Takagi, Exceptional Procedure Attack on Elliptic Curve Cryptosystems, PKC 2003, pp.224-239, 2003.
DOI : 10.1007/3-540-36288-6_17

M. Izumi, J. Ikegami, K. Sakiyama, and K. Ohta, Improved countermeasure against Address-bit DPA for ECC scalar multiplication, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.981-984, 2010.
DOI : 10.1109/DATE.2010.5456907

A. Jakulin and I. Bratko, Analyzing Attribute Dependencies, PKDD 2003, volume 2838 of LNAI, pp.229-240, 2003.
DOI : 10.1007/978-3-540-39804-2_22

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.14.7148

M. Joye, Defences Against Side-Channel Analysis, p.39, 2005.
DOI : 10.1017/CBO9780511546570.007

M. Joye and J. Quisquater, Hessian Elliptic Curves and Side-Channel Attacks, Cryptographic Hardware and Embedded Systems, pp.402410-402444, 2001.
DOI : 10.1007/3-540-44709-1_33

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.1196

M. Joye and C. Tymen, Protections against Differential Analysis for Elliptic Curve Cryptography ??? An Algebraic Approach ???, CHES, pp.377-390, 2001.
DOI : 10.1007/3-540-44709-1_31

M. Joye and S. Yen, The Montgomery Powering Ladder, CHES, pp.291-302, 2002.
DOI : 10.1007/3-540-36400-5_22

W. Edward, J. Kamen, and . Su, Introduction to optimal estimation, Advanced textbooks in control and signal processing, Control and Signal Processing Series, p.143, 1999.

J. Kaps and R. Velegalati, DPA Resistant AES on FPGA Using Partial DDL, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.273-280, 2010.
DOI : 10.1109/FCCM.2010.49

M. Karpovsky, K. J. Kulikowski, and A. Taubin, Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard, International Conference on Dependable Systems and Networks, 2004, pp.93-101, 2004.
DOI : 10.1109/DSN.2004.1311880

R. Karri, K. Wu, P. Mishra, and Y. Kim, Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.21, issue.12, pp.1509-1517, 2002.

M. Kasper, W. Schindler, and M. Stöttinger, A stochastic method for security evaluation of cryptographic FPGA implementations, 2010 International Conference on Field-Programmable Technology, pp.146-153, 2010.
DOI : 10.1109/FPT.2010.5681772

C. Kim, J. Shin, J. Quisquater, and P. Lee, Safe-error attack on spafa resistant exponentiations using a hw modular multiplier, Information Security and Cryptology -ICISC 2007, pp.273-281, 2007.

C. Paul, J. Kocher, B. Jaffe, and . Jun, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Proceedings of CRYPTO'96PDF). 3, 4, 6, pp.104-113, 1996.

C. Paul, J. Kocher, and B. Jaffe, Differential Power Analysis, CRYPTO, volume 1666 of LNCS, pp.388-397, 1999.

C. Paul, J. Kocher, and B. Jaffe, Differential Power Analysis, Proceedings of CRYPTO'99, pp.388-397, 1999.

Y. Komano, H. Shimizu, and S. Kawamura, Built-in determined subkey correlation power analysis, Cryptology ePrint Archive Report, vol.161161, p.137, 2009.

O. Kömmerling and M. G. Kuhn, Design principles for tamper-resistant smartcard processors, Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology, pp.2-2, 1999.

B. Köpf and D. Basin, An information-theoretic model for adaptive side-channel attacks, Proceedings of the 14th ACM conference on Computer and communications security , CCS '07, pp.286-296, 2007.
DOI : 10.1145/1315245.1315282

K. J. Kulikowski, M. G. Karpovsky, and A. Taubin, Power Attacks on Secure Hardware Based on Early Propagation of Data, 12th IEEE International On-Line Testing Symposium (IOLTS'06), pp.131-138, 2006.
DOI : 10.1109/IOLTS.2006.49

T. Le, J. Clédière, C. Canovas, B. Robisson, C. Servière et al., A Proposition for Correlation Power Analysis Enhancement, CHES, pp.174-186, 2006.
DOI : 10.1007/11894063_14

URL : https://hal.archives-ouvertes.fr/hal-00133098

Y. Li, K. Sakiyama, L. Batina, D. Nakatsu, and K. Ohta, Power Variance Analysis breaks a masked ASIC implementation of AES, DATE, pp.1059-1064

V. Lomné, A. Dehbaoui, P. Maurine, L. Torres, and M. Robert, Differential Power Analysis enhancement with statistical preprocessing, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 0152.
DOI : 10.1109/DATE.2010.5457007

Y. Lu, M. P. Neill, and J. V. Mccanny, FPGA implementation and analysis of random delay insertion countermeasure against DPA, 2008 International Conference on Field-Programmable Technology, pp.201-208, 2008.
DOI : 10.1109/FPT.2008.4762384

J. Lv and Y. Han, Enhanced DES implementation secure against differential power analysis in smart-cards, Information Security and Privacy, 10th Australasian Conference, pp.195-206, 2005.

H. Maghrebi, J. Danger, F. Flament, and S. Guilley, Evaluation of Countermeasures Implementation Based on Boolean Masking to Thwart First and Second Order Side-Channel Attacks, SCS, IEEE, pp.1-6, 2009.

H. Maghrebi, S. Guilley, J. Danger, and F. Flament, Entropybased Power Attack, HOST, pp.1-6, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00618482

P. Maistri and R. Leveugle, Double-data-rate computation as a countermeasure against fault analysis. Computers, IEEE Transactions on, vol.57, issue.11, pp.1528-1539, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00348325

H. Mamiya, A. Miyaji, and H. Morimoto, Secure Elliptic Curve Exponentiation against RPA, ZRA, DPA, and SPA, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.89, issue.8, pp.89-2207, 2006.
DOI : 10.1093/ietfec/e89-a.8.2207

S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards, p.18, 2006.

S. Mangard, E. Oswald, and F. Standaert, One for All -All for One: Unifying Standard DPA Attacks, Cryptology ePrint Archive Report, vol.449, p.133, 2009.

R. P. Mcevoy, C. C. Murphy, W. P. Marnane, and M. Tunstall, Isolated WDDL, ACM Transactions on Reconfigurable Technology and Systems, vol.2, issue.1, pp.1-23, 2009.
DOI : 10.1145/1502781.1502784

N. Mentens, L. Batina, B. Preneel, and I. Verbauwhede, An fpga implementation of rijndael: Trade-offs for side-channel security, p.101, 2004.

S. Thomas and . Messerges, Securing the AES Finalists Against Power Analysis Attacks, Fast Software Encryption'00, pp.150-164, 2000.

T. S. Messerges, E. A. Dabbish, and R. H. Sloan, Investigations of Power Analysis Attacks on Smartcards, USENIX ? Smartcard'99, pp.151-162, 1999.

T. S. Messerges, E. A. Dabbish, and R. H. Sloan, Examining smart-card security under the threat of power analysis attacks, IEEE Transactions on Computers, vol.51, issue.5, pp.541-552, 2002.
DOI : 10.1109/TC.2002.1004593

L. Peter and . Montgomery, Speeding the Pollard and Elliptic Curve Methods of Factorization, Mathematics of Computation, vol.48, issue.177, pp.243-264, 1987.

E. De-mulder, B. Gierlichs, B. Preneel, and I. Verbauwhede, Practical DPA Attacks on MDPL In First International Workshop on Information Forensics and Security (WIFS), IEEE Signal Processing Society, vol.231, issue.28, p.29, 2009.

F. Muller and F. Valette, High-Order Attacks Against the Exponent Splitting Protection, Public Key Cryptography -PKC 2006, 9th International Conference on Theory and Practice of Public-Key Cryptography, pp.315-329, 2006.
DOI : 10.1007/11745853_21

H. N. Nagaraja, Functions of concomitants of order statistics, Journal of the Indian Society for Probability and Statistics, vol.7, pp.15-32, 2003.

M. Nassar, S. Guilley, and J. Danger, Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks ? Complete version, Cryptology ePrint Archive Report, vol.534534, p.112, 2011.

E. Oswald, S. Mangard, and N. Pramstaller, Secure and efficient masking of aes -a mission impossible? Cryptology ePrint Archive, Report, vol.134, p.20, 2004.

E. Oswald, S. Mangard, N. Pramstaller, and V. Rijmen, A Side-Channel Analysis Resistant Description of the AES S-Box, Proceedings of FSE'05, pp.413-423, 2005.
DOI : 10.1007/11502760_28

E. Oswald and K. Schramm, An Efficient Masking Scheme for AES Software Implementations, WISA'05, pp.292-305, 1921.
DOI : 10.1007/11604938_23

A. D. Oviedo, On fault-based attacks and countermeasures for elliptic curve cryptosystems, p.44, 2008.

G. Piret and J. Quisquater, A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad, CHES, pp.77-88, 2003.
DOI : 10.1007/978-3-540-45238-6_7

G. Piret and F. Standaert, Security Analysis of Higher-Order Boolean Masking Schemes for Block Ciphers (with Conditions of Perfect Masking) IET Information Security, pp.1-11, 2008.

T. Popp, M. Kirschbaum, T. Zefferer, and S. Mangard, Evaluation of the Masked Logic Style MDPL on a Prototype Chip, CHES, pp.81-94, 2007.
DOI : 10.1007/978-3-540-74735-2_6

T. Popp and S. Mangard, Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints, Proceedings of CHES'05, pp.172-186, 2005.
DOI : 10.1007/11545262_13

E. Prouff and M. Rivain, A Generic Method for Secure SBox Implementation, Lecture Notes in Computer Science, vol.4867, issue.20, pp.227-244, 2007.
DOI : 10.1007/978-3-540-77535-5_17

E. Prouff and M. Rivain, Theoretical and Practical Aspects of Mutual Information Based Side Channel Analysis, LNCS, vol.5536, pp.499-518, 2009.

E. Prouff and M. Rivain, Theoretical and Practical Aspects of Mutual Information Based Side Channel Analysis, IJACT, 2010.

E. Prouff, M. Rivain, and R. Bevan, Statistical Analysis of Second Order Differential Power Analysis, IEEE Transactions on Computers, vol.58, issue.6, pp.799-811, 2009.
DOI : 10.1109/TC.2009.15

J. Quisquater and D. Samyde, Eddy current for Magnetic Analysis with Active Sensor, p.14, 2002.

C. Rechberger and E. Oswald, Practical Template Attacks, WISA, pp.443-457, 2004.
DOI : 10.1007/978-3-540-31815-6_35

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.126.6474

F. Regazzoni, Y. Wang, and F. Standaert, FPGA Implementations of the AES Masked Against Power Analysis Attacks, In COSADE, vol.21, issue.23, pp.56-66, 2011.

M. Rivain, E. Dottax, and E. Prouff, Block ciphers implementations provably secure against second order side channel analysis. Fast Software Encryption FSE, pp.127-143, 2008.
DOI : 10.1007/978-3-540-71039-4_8

M. Rivain and E. Prouff, Provably Secure Higher-Order Masking of AES, CHES, pp.413-427, 2010.
DOI : 10.1007/978-3-642-15031-9_28

M. Saeki and D. Suzuki, Security Evaluations of MRSL and DRSL Considering Signal Delays IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, issue.1, pp.91-176, 2008.

S. Gilbert, Probabilités analyse des données et statistiques, p.133, 2008.

L. Sauvage, S. Guilley, and Y. Mathieu, Electromagnetic Radiations of FPGAs, ACM Transactions on Reconfigurable Technology and Systems, vol.2, issue.1, pp.1-24, 2009.
DOI : 10.1145/1502781.1502785

URL : https://hal.archives-ouvertes.fr/hal-00319164

P. Schaumont and K. Tiri, Masking and Dual-Rail Logic Don???t Add Up, CHES, pp.95-106, 2007.
DOI : 10.1007/978-3-540-74735-2_7

E. Schechtman and S. Yitzhaki, A Measure Of Association Based On Gin's Mean Difference, Communications in Statistics - Theory and Methods, vol.72, issue.5, pp.207-231, 1987.
DOI : 10.1214/aoms/1177706210

W. Schindler, A Timing Attack against RSA with the Chinese Remainder Theorem, CHES, pp.109-124, 1965.
DOI : 10.1007/3-540-44499-8_8

W. Schindler, A Combined Timing and Power Attack, Lecture Notes in Computer Science, vol.2274, pp.263-279, 2002.
DOI : 10.1007/3-540-45664-3_19

W. Schindler, Advanced stochastic methods in side channel analysis on block ciphers in the presence of masking ISSN (Online) 1862-2984, ISSN (Print), Journal of Mathematical Cryptology, vol.2, issue.9, pp.291-310, 2008.

W. Schindler, F. Koeune, and J. Quisquater, Improving Divide and Conquer Attacks against Cryptosystems by Better Error Detection / Correction Strategies, Cryptography and Coding, pp.245-267, 2001.
DOI : 10.1007/3-540-45325-3_22

W. Schindler, K. Lemke, and C. Paar, A Stochastic Model for Differential Side Channel Cryptanalysis, LNCS LNCS, vol.3659, pp.30-46
DOI : 10.1007/11545262_3

K. Schramm and C. Paar, Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, and Jean-Luc Dan- ger. WDDL is Protected Against Setup Time Violation Attacks, Higher Order Masking of the AES FDTC conjunction with CHES'09, pp.208-225, 2006.

S. Shah, R. Velegalati, J. Kaps, and D. Hwang, Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs, 2010 International Conference on Reconfigurable Computing and FPGAs, pp.274-279, 2010.
DOI : 10.1109/ReConFig.2010.80

J. Shlens, A tutorial in Principal Component Analysis Available online on 10 decembre, p.133, 2005.

C. Sinz, Towards an Optimal CNF Encoding of Boolean Cardinality Constraints, Lecture Notes in Computer Science, vol.3709, pp.827-831, 2005.
DOI : 10.1007/11564751_73

S. Kolenikov and G. Angeles, The use of discrete data in PCA for socio-economic status evaluation Available online on 2 february, p.133, 2005.

S. Skorobogatov, Synchronization method for SCA and fault attacks, Journal of Cryptographic Engineering, vol.34, issue.3, pp.71-77
DOI : 10.1007/s13389-011-0004-0

S. Skorobogatov and R. Anderson, Optical Fault Induction Attacks, Cryptographic Hardware and Embedded Systems -CHES 2002, pp.31-48, 2003.
DOI : 10.1007/3-540-36400-5_2

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.9.5680

I. Lindsay and . Smith, A tutorial in Principal Component Analysis Available online on 26 february, p.133, 2002.

R. Soares, N. Calazans, V. Lomné, P. Maurine, L. Torres et al., Evaluating the robustness of secure triple track logic through prototyping, Proceedings of the twenty-first annual symposium on Integrated circuits and system design, SBCCI '08, pp.193-198, 2008.
DOI : 10.1145/1404371.1404425

URL : https://hal.archives-ouvertes.fr/lirmm-00373516

M. Soos, SAT-solver " cryptominisat, 2011.

M. Soos, K. Nohl, and C. Castelluccia, Extending SAT Solvers to Cryptographic Problems, Lecture Notes in Computer Science, vol.39, issue.2, pp.244-257, 2009.
DOI : 10.1007/s10817-007-9074-1

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.157.4807

F. Standaert, B. Gierlichs, and I. Verbauwhede, Partition vs. Comparison Side-Channel Distinguishers: An Empirical Evaluation of Statistical Tests for Univariate Side-Channel Attacks against Two Unprotected CMOS Devices, ICISC, pp.253-267, 2008.
DOI : 10.1007/11802839_42

F. Standaert, T. Malkin, and M. Yung, A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks, EUROCRYPT, pp.443-461, 2009.
DOI : 10.1007/978-3-540-85053-3_26

F. Standaert, É. Peeters, F. Macé, and J. Quisquater, Updates on the Security of FPGAs Against Power Analysis Attacks, ARC, pp.335-346, 2006.
DOI : 10.1007/11802839_42

F. Standaert, F. Koeune, and W. Schindler, How to Compare Profiled Side-Channel Attacks?, Applied Cryptography and Network Security, pp.485-498, 2009.
DOI : 10.1007/978-3-642-01957-9_30

F. Standaert, G. Rouvroy, and J. Quisquater, FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks, 2006 International Conference on Field Programmable Logic and Applications, p.95, 2006.
DOI : 10.1109/FPL.2006.311315

D. Stebila and N. Thériault, Unified Point Addition Formul?? and Side-Channel Attacks, CHES, p.34, 2006.
DOI : 10.1007/11894063_28

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.415.4515

D. Suzuki and M. Saeki, Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style, CHES, pp.255-269, 2006.
DOI : 10.1007/11894063_21

K. Tiri and I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.246-251, 2004.
DOI : 10.1109/DATE.2004.1268856

K. Tiri and I. Verbauwhede, Place and Route for Secure Standard Cell Design, Proceedings of WCC / CARDIS, pp.143-158, 2004.
DOI : 10.1007/1-4020-8147-2_10

K. Tiri and I. Verbauwhede, A digital design flow for secure integrated circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.7, pp.1197-1208, 2006.
DOI : 10.1109/TCAD.2005.855939

R. Toth, Z. Faigl, M. Szalay, and S. Imre, An advanced timing attack scheme on rsa, Telecommunications Network Strategy and Planning Symposium The 13th International, pp.1-24, 2008.
DOI : 10.1109/netwks.2008.4763727

E. Trichina and A. Bellezza, Implementation of Elliptic Curve Cryptography with Built-In Counter Measures against Side Channel Attacks, Cryptographic Hardware and Embedded Systems -CHES 2002, pp.297-312, 2003.
DOI : 10.1007/3-540-36400-5_9

E. Trichina, D. D. Seta, and L. Germani, Simplified Adaptive Multiplicative Masking for AES, Cryptographic Hardware and Embedded Systems -CHES 2002, pp.71-85, 2003.
DOI : 10.1007/3-540-36400-5_15

S. Tufféry and G. Saporta, Data mining et statistique décisionnelle. L'intelligence des données, pp.978271080946-3, 2010.

R. Velegalati and J. Kaps, Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs, 2011 21st International Conference on Field Programmable Logic and Applications, pp.506-511, 2011.
DOI : 10.1109/FPL.2011.100

N. Veyrat-charvillon and F. Standaert, Mutual Information Analysis: How, When and Why?, CHES, pp.429-443, 2009.
DOI : 10.1007/978-3-642-04138-9_30

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.178.6511

N. Veyrat-charvillon and F. Standaert, Adaptive Chosen-Message Side-Channel Attacks, ACNS, pp.186-199, 2010.
DOI : 10.1007/978-3-642-13708-2_12

J. Waddle and D. Wagner, Towards Efficient Second-Order Power Analysis, CHES, pp.1-15, 2004.
DOI : 10.1007/978-3-540-28632-5_1

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.460.2991

C. D. Walter, Simple Power Analysis of Unified Code for ECC Double and Add, pp.86-115, 2004.
DOI : 10.1007/978-3-540-28632-5_14

B. Chih-hsu-yen and . Wu, Simple error detection methods for hardware implementation of Advanced Encryption Standard, IEEE Transactions on Computers, vol.55, issue.6, pp.720-731, 2006.
DOI : 10.1109/TC.2006.90

S. Yen and M. Joye, Checking before output may not be enough against fault-based cryptanalysis, IEEE Trans. Comput, vol.49, issue.9, pp.967-970, 2000.

S. Yitzhaki, Gini's mean difference: a superior measure of variability for nonnormal distributions, International Journal of Statistics, vol.2, pp.285-316, 2003.

P. Yu and P. Schaumont, Secure FPGA circuits using controlled placement and routing, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis , CODES+ISSS '07, pp.45-50, 2007.
DOI : 10.1145/1289816.1289831

H. Zeng-guang, PCA for data fusion and navigation of mobile robots, LNCS, vol.3495, pp.610-611, 2005.