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Reliability analysis methods and improvement techniques applicable to digital circuits

Abstract : With the current advances achieved in the manufacturing process of integrated circuits, a series of reliability-threatening mechanisms have emerged or have become more prominent. For instance, physical defects originating from poorly lithographed wires, vias and other low-level devices are commonly seen in nanometric circuits. On the other hand, circuits have also become more sensitive to the strikes of highly energized particles. Both mechanisms, although essentially different, can cause multiple faults that contribute for lower reliabilities in integrated circuits. Multiple faults are more troubling than single faults since these are more severe and also because they can overcome fault tolerance techniques. Digital circuits are used in most electronic systems nowadays, but there is a specific context in which they are required to be reliable. Such context comprises high-dependability applications. This is the scenario in which this thesis is conceived. It’s goals are twofold : (a) to pro pose methods to assess the reliability of digital circuits, and (b) to propose techniques for reliability improvement. Concerning the first goal, several methods have been proposed in the literature and the text shows how these methods present limitations with respect to circuit size (number of gates), circuit type (sequential or combinational) and fault profile (single versus multiple faults). This thesis proposes two methods for reliability assessment. The first method is termed SPR+ and its targeted at the analysis of combinational logic only. SPR+ improves the average analysis accuracy by taking into account the effect of each fanout reconvergent node to the overall circuit reliability. Another method, termed SNaP, is also proposed in this thesis. It is a hybrid approach since it is partially based on simulation. SNaP can be used for combinational and sequential logic and can also be emulated in an FPGA device for faster analysis. Both SPR+ and SNaP can cope with multiple faults.
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Submitted on : Tuesday, September 8, 2015 - 2:53:06 PM
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  • HAL Id : tel-01195815, version 1



Samuel Nascimento Pagliarini. Reliability analysis methods and improvement techniques applicable to digital circuits. Electronics. Télécom ParisTech, 2013. English. ⟨NNT : 2013ENST0060⟩. ⟨tel-01195815⟩



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