N. , H. Ardening:-a-h-euristic-based-locality, H. Bias-for-selective, and .. Ultiple-faults, 106 4.2.1 Introducing a H euristic-Based Locality Bias

P. Ling, C. Function, and .. , 117 4.3.1 Sum of Elements H euristic 119 4.3.2 Percent Wise H euristic, p.122

C. Nalyse-du-nombre-différentdiff´différent-de-fanouts, 17 14 Impact des noeuds basées sur les valeurs D (f ), p.17

S. Comparaison-entre-les-deux-heuristiques and S. , (a) comportement fonctionnel d'un inverseur ; (b) modélisationmod´modélisation SN aP, p.16

S. Comparaison-entre and .. , 22 22 Valeurs de puissance normalisées pour le durcissement sélectif avec et sans affi niténit´nité, p.25

S. Spr, Execution times for 100 runs using, p.86

A. Saha, N. , J. Es-a-n-d, and . Ba, Digital Principles and Logic Design, ser. Infi nity Science Series, 2009.

D. Gajski, Principles of Digital Design, ser. Prentice H all International Editions, 1997.

M. H. Utton, R. Yuan, J. Schleicher, G. Baeckler, S. Cheung et al., A M ethodology for FPGA to Structured-A SIC Synthesis and Verifi cation, Proceedings of theconferenceon Design, automation and test in Europe(DATE), pp.64-69, 2006.

A. Avizienis, J. Laprie, B. Randell, and V. , Fundamental Concepts of Dependability, 2000.

J. A. Zambuja, S. Pagliarini, L. Rosa, and F. Kastensmidt, Exploring the Limitations of Softw are-based Techniques in SEE Fault Coverage, Journal of Electronic Testing Theory and Applications, pp.1-10, 2011.

R. Baumann, Soft Errors in A dvanced Semiconductor Devices-part I: the three Radiation Sources Device and M aterials Reliability, IEEE Transactions on, vol.1, issue.1, pp.17-22, 2001.

T. J. O-'gorman, J. M. Ross, A. H. Taber, J. F. Ziegler, H. P. Uhlfeld et al., Field testing for cosmic ray soft errors in semiconductor memories, IBM Journal of Research and Development, vol.40, issue.1, pp.41-50, 1996.
DOI : 10.1147/rd.401.0041

R. D. Eldred, Test Routines Based on Symbolic Logical Statements, Journal of the ACM, vol.6, issue.1, pp.33-37, 1959.
DOI : 10.1145/320954.320957

J. M. Galey, R. E. , and J. P. Roth, Techniques for the diagnosis of sw itching circuit failures, Switching Circuit Theory and Logical Design (SWCT). Proceedings of theSecond Annual Symposium on, oct, pp.152-160, 1961.

M. Bushnell and V. , M emory and M ixed-Signal VLSI Circuits, Essentials of Electronic Testing for Digital, pp.57-80, 2002.

C. Stapper, F. , and K. Saji, Integrated circuit yield statistics, Proceedings of theIEEE, pp.453-470, 1983.
DOI : 10.1109/PROC.1983.12619

I. Koren and Z. Koren, Defect Tolerance in VLSI Circuits, Proceedings of theIEEE, pp.1819-1838, 1998.
DOI : 10.1016/B978-012088525-1/50011-0

B. Benw-are, C. Schuermyer, M. Sharma, and T. H. Errmann, </title> </titles> <publication_date> <month>02</month> <year>2012</year> </publication_date> <pages> <first_page>64</first_page> <last_page>64</last_page> </pages> <publisher_item> <item_number item_number_type='arNumber'>6198433</item_number> </publisher_item> <doi_data> <doi>10.1109/MDT.2012.2196611</doi> <resource>http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6198433</resource> </doi_data> </journal_article> <journal_article> <titles> <title><![CDATA[</title> </titles> <publication_date> <month>02</month> <year>2012</year> </publication_date> <pages> <first_page>72</first_page> <last_page>72</last_page> </pages> <publisher_item> <item_number item_number_type='arNumber'>6198434</item_number> </publisher_item> <doi_data> <doi>10.1109/MDT.2012.2196612</doi> <resource>http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6198434</resource> </doi_data> </journal_article> <journal_article> <titles> <title><![CDATA[</title> </titles> <publication_date> <month>02</month> <year>2012</year> </publication_date> <pages> <first_page>79</first_page> <last_page>79</last_page> </pages> <publisher_item> <item_number item_number_type='arNumber'>6198435</item_number> </publisher_item> <doi_data> <doi>10.1109/MDT.2012.2196613</doi> <resource>http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6198435</resource> </doi_data> </journal_article> <journal_article> <titles> <title><![CDATA[Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results, IEEE Design & Test of Computers, vol.29, issue.1, pp.8-18, 2012.
DOI : 10.1109/MDT.2011.2178386

F. Ferguson, M. Taylor, and T. Larrabee, Testing for Parametric Faults in Static CM OS Circuits, Test Conference. Proceedings of the International, pp.436-443, 1990.

F. Sexton, Destructive single-event effects in semiconductor devices and ICs, IEEE Transactions on Nuclear Science, vol.50, issue.3, pp.603-621, 2003.
DOI : 10.1109/TNS.2003.813137

J. Schw-ank, V. Ferlet-cavrois, M. R. Shaneyfelt, P. Paillet, and P. Dodd, Radiation effects in SOI technologies, IEEE Transactions on Nuclear Science, vol.50, issue.3, pp.522-538, 2003.
DOI : 10.1109/TNS.2003.812930

P. E. Dodd and L. W. , Basic mechanisms and modeling of single-event upset in digital microelectronics, IEEE Transactions on Nuclear Science, vol.50, issue.3, pp.583-602, 2003.
DOI : 10.1109/TNS.2003.813129

N. Seifert, Radiation-induced Soft Errors: A Chip-level Modeling Perspective, Foundations and Trends?? in Electronic Design Automation, vol.11, issue.2-3, pp.99-221
DOI : 10.1561/1000000018

S. V. Li, P. Dve, J. A. Bose, and . Rivers, Online Estimation of A rchitectural Vulnerability Factor for Soft Errors, Symposium on Computer Architecture, Proceedings of the 35th Annual International (ISCA). IEEE Computer Society, pp.341-352, 2008.

T. Karnik and P. , Characterization of soft errors caused by single event upsets in CMOS processes, IEEE Transactions on Dependable and Secure Computing, vol.1, issue.2, pp.128-143, 2004.
DOI : 10.1109/TDSC.2004.14

H. Guyen and Y. , A Systematic A pproach to SER Estimation and Solutions, Reliability Physics Symposium (IRPS). Proceedings of the 41st Annual IEEE International, pp.60-70, 2003.

P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. A. Lvisi, M odeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic, Dependable Systems and Networks (DSN). Proceedings of the International Conference on, pp.389-398, 2002.

A. Dixit and A. Wood, The impact of new technology on soft error rates, 2011 International Reliability Physics Symposium, pp.5-9, 2011.
DOI : 10.1109/IRPS.2011.5784522

M. Casey, A. Duncan, B. Bhuva, W. Robinson, and L. , Simulation Study on the Effect of Multiple Node Charge Collection on Error Cross-Section in CMOS Sequential Logic, IEEE Transactions on Nuclear Science, vol.55, issue.6, pp.3136-3140, 2008.
DOI : 10.1109/TNS.2008.2005895

S. Pagliarini, F. Kastensmidt, L. Entrena, A. Lindoso, and E. M. Illan, Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits, IEEE Transactions on Nuclear Science, vol.58, issue.6, pp.2768-2775, 2011.
DOI : 10.1109/TNS.2011.2168239

J. A. Hlbin, L. , B. Bhuva, B. , M. Gadlage et al., Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits, IEEE Transactions on Nuclear Science, vol.56, issue.6, pp.3050-3056, 2009.
DOI : 10.1109/TNS.2009.2033689

N. Seifert, X. Zhu, and L. , Impact of scaling on soft-error rates in commercial microprocessors, IEEE Transactions on Nuclear Science, vol.49, issue.6, pp.3100-3106, 2002.
DOI : 10.1109/TNS.2002.805402

P. Liden, P. Dahlgren, R. Johansson, and J. Karlsson, On Latching Probability of Particle Induced Transients in Combinational N etw orks, Fault-Tolerant Computing (FTCS). Digest of Papers from the Twenty-Fourth International Symposium on, pp.340-349, 1994.

M. Baze and S. Buchner, Attenuation of single event induced pulses in CMOS combinational logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2217-2223, 1997.
DOI : 10.1109/23.659038

R. Ramanarayanan, V. Degalahal, R. Krishnan, J. Kim, V. et al., M odeling Soft Errors at the Device and Logic Levels for Combinational Circuits, Dependable and Secure Computing, pp.202-216, 2009.

N. George and J. Lach, Characterization of Logical M asking and Error Propagation in Combinational Circuits and Effects on System Vulnerability, Dependable Systems Networks (DSN), IEEE/IFIP 41st International Conference on, pp.323-334, 2011.

F. Wang, Y. Xie, R. Rajaraman, and B. Vaidyanathan, Soft Error Rate A nalysis for Combinational Logic Using A n A ccurate Electrical M asking M odel, VLSI Design , 2007 (VLSID). 20th International Conferenceon, pp.165-170, 2007.

R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, A n Effi cient Static A lgorithm for Computing the Soft Error Rates of Combinational Circuits, Design, Automation and Test in Europe(DATE). Proceedings of the, pp.1-6, 2006.

S. Krishnasw-amy, I. L. , and J. P. , On the Role of Timing M asking in Reliable Logic Circuit Design, Design Automation Conference(DAC) Proceedings of the 45th annual. A CM, pp.924-929, 2008.

E. Czeck and D. Siew-iorek, Effects of transient gate-level faults on program behavior, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium, pp.236-243, 1990.
DOI : 10.1109/FTCS.1990.89371

S. Kim and A. Somani, Soft Error Sensitivity Characterization for M icroprocessor Dependability Enhancement Strategy, Dependable Systems and Networks (DSN). Proceedings of theInternational Conferenceon, pp.416-425, 2002.

X. Li, S. Dve, P. Bose, and J. Rivers, SoftA rch: an A rchitecture-level Tool for M odeling and A nalyzing Soft Errors, Dependable Systems and Networks (DSN). Proceedings of theInternational Conferenceon, pp.496-505, 2005.

K. R. Walcott, G. , and S. Gurumurthi, Dynamic Prediction of A rchitectural Vulnerability from M icroarchitectural State

D. T. Franco, FiabilitéFiabilit´Fiabilité du Signal des Circuits Logiques Combinatoires sous Fautes SimultanéesSimultan´Simultanées M ultiples, 2009.

W. Kuo, Reliability Enhancement Through Optimal Burn-In, IEEE Transactions on Reliability, vol.33, issue.2, pp.145-156, 1984.
DOI : 10.1109/TR.1984.5221760

X. Li, J. Qin, and J. Bernstein, Compact M odeling of M OSFET Wearout M echanisms for Circuit-Reliability Simulation Device and M aterials Reliability, IEEE Transactions on, vol.8, issue.1, pp.98-121, 2008.

M. H. Sueh, T. Tsai, and R. Iyer, Fault Injection Techniques and Tools, Computer, vol.30, issue.4, pp.75-82, 1997.

J. Clark and D. Pradhan, Fault injection: a method for validating computer-system dependability, Computer, vol.28, issue.6, pp.47-56, 1995.
DOI : 10.1109/2.386985

E. Jenn, J. Rlat, M. Rimen, J. Ohlsson, and J. Karlsson, Fault Injection into VH DL M odels: the M EFISTO Tool, Fault-Tolerant Computing (FTCS). Digest of Papers from theTwenty-Fourth International Symposium on, pp.66-75, 1994.

L. , A. Baranski, D. Van, N. Ort, J. Eng et al., A nalysis of Singleevent Effects in Combinational Logic-simulation of the A M 2901 Bitslice Processor, Nuclear Science IEEE Transactions on, vol.47, issue.6, pp.2609-2615, 2000.

S. Rezgui, G. Sw-ift, R. Velazco, and F. Farmanesh, Validation of an SEU simulation technique for a complex processor: PowerPC7400, IEEE Transactions on Nuclear Science, vol.49, issue.6, pp.3156-3162, 2002.
DOI : 10.1109/TNS.2002.805982

URL : https://hal.archives-ouvertes.fr/hal-00008201

M. Valderas, P. Peronnard, C. Lopez-ongil, R. Ecoffet, F. Bezerra et al., Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors, IEEE Transactions on Nuclear Science, vol.54, issue.4, pp.924-928, 2007.
DOI : 10.1109/TNS.2007.893871

URL : https://hal.archives-ouvertes.fr/hal-00174506

J. A. Rlat, M. A. Guera, L. Mat, Y. Crouzet, J. Fabre et al., Fault Injection for Dependability Validation: a M ethodology and Some A pplications, Software Engineering IEEE Transactions on, vol.16, issue.2, pp.166-182, 1990.

J. Karlsson, P. Liden, P. Dahlgren, R. Johansson, and U. Gunnefl-o, Using H eavyion Radiation to Validate Fault-handling M echanisms, pp.8-23, 1994.

S. , J. H. , and C. Wu, Sequential Circuit Fault Simulation Using Logic Emulation Computer-Aided Design of Integrated Circuitsand Systems, IEEE Transactions on, vol.17, issue.8, pp.724-736, 1998.

P. Civera, L. , M. Rebaudengo, M. Reorda, and M. Violante, Exploiting circuit emulation for fast hardness evaluation, IEEE Transactions on Nuclear Science, vol.48, issue.6, pp.2210-2216, 2001.
DOI : 10.1109/23.983197

M. A. Guirre, V. Baena, J. Tombs, and M. Violante, A N ew A pproach to Estimate the Effect of Single Event Transients in Complex Circuits, Nuclear Science IEEE Transactions on, vol.54, issue.4, pp.1018-1024, 2007.

C. Lopez-ongil, M. Garcia-valderas, M. Portela-garcia, and L. Entrena, Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation, IEEE Transactions on Nuclear Science, vol.54, issue.1, pp.252-261, 2007.
DOI : 10.1109/TNS.2006.889115

L. Entrena, M. Garcia-valderas, R. Fernandez-cardenal, A. Lindoso, M. Portela et al., Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection, IEEE Transactions on Computers, vol.61, issue.3, pp.313-322, 2012.
DOI : 10.1109/TC.2010.262

P. Sedcole, B. Blodget, T. Becker, J. , and P. Lysaght, M odular Dynamic Reconfi guration in Virtex FPGA s, Computersand Digital Techniques, IEE Proceedings, pp.157-164, 2006.

L. A. Ntoni, R. Leveugle, and B. Feher, Using Run-time Reconfi guration for Fault Injection in H ardw are Prototypes, Defect and Fault Tolerance in VLSI Systems Proceedings. 17th IEEE International Symposium on, pp.245-253, 2002.

L. , J. , G. Goncalves-dos-santos-junior, E. Crespo, M. et al., FIFA : A Fault-injection-fault-analysis-based Tool for Reliability A ssessment at RTL Level, M icroelectronics Reliability, vol.51, pp.9-11, 2011.

M. De-vasconcelos, D. Franco, L. De, B. , and J. , Reliability A nalysis of Combinational Circuits Based on a Probabilistic Binomial M odel, Circuits and Systems and TAISA Conference (NEWCAS-TAISA). Joint 6th International IEEE Northeast Workshop on, pp.310-313, 2008.

J. Partridge, E. C. , and L. D. , The A pplication of Failure A nalysis in Procuring and Screening of Integrated Circuits, Physics of Failure in Electronics Fourth Annual Symposium on the, pp.95-139, 1965.

J. A. Utran, P. Roche, J. Borel, C. Sudre, K. Castellani-coulie et al., Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130 nm SRAM, IEEE Transactions on Nuclear Science, vol.54, issue.4, pp.1002-1009, 2007.
DOI : 10.1109/TNS.2007.891398

Z. Torok, S. Platt, and C. X. Xiao, SEE-inducing Effects of Cosmic Rays at the H igh- A ltitude Research Station Jungfraujoch Compared to A ccelerated Test Data, Radiation and Its Effects on Components and Systems, pp.1-6, 2007.

S. Buchner, M. Baze, D. Brow-n, D. , and J. M. Elinger, Comparison of error rates in combinational and sequential logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2209-2216, 1997.
DOI : 10.1109/23.659037

A. Chugg, J. Ward, J. Cintosh, N. Flynn, P. Duncan et al., Improved Fine-scale Laser M apping of Component SEE Sensitivity, Radiation and Its Effects on Components and Systems (RADECS) 12th European Conference on, pp.442-448, 2011.

E. Cannon, M. Cabanas-h-olmen, J. Wert, T. Mort, R. Brees et al., H eavy Ion, H igh-Energy, and Low -Energy Proton SEE Sensitivity of 90-nm RH BD SRA M s, Nuclear Science IEEE Transactions on, vol.57, issue.6, pp.3493-3499, 2010.

P. Rech, J. Galliere, P. Girard, A. Griffoni, J. Boch et al., N eutron-induced M ultiple Bit Upsets on Dynamically-stressed Commercial SRA M A rrays, Radiation and Its Effects on Components and Systems (RADECS), 12th European Conferenceon, pp.274-280, 2011.

J. Schw-ank, M. Shaneyfelt, J. Baggio, P. Dodd, J. Felix et al., Effects of particle energy on proton-induced single-event latchup, IEEE Transactions on Nuclear Science, vol.52, issue.6, pp.2622-2629, 2005.
DOI : 10.1109/TNS.2005.860672

B. Sieraw-ski, M. , R. Reed, M. Clemens, R. Weller et al., M uon-Induced Single Event Upsets in Deep-Submicron Technology, Nuclear Science IEEE Transactions on, vol.57, issue.6, pp.3273-3278, 2010.

G. Gasiot, D. Giot, and P. Roche, Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65 nm CMOS Technology, IEEE Transactions on Nuclear Science, vol.53, issue.6, pp.3479-3486, 2006.
DOI : 10.1109/TNS.2006.885007

C. Gelderloos, R. J. Peterson, M. N. Elson, and J. Ziegler, Pion-induced soft upsets in 16 mbit DRAM chips, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2237-2242, 1997.
DOI : 10.1109/23.659041

K. N. Patel, I. L. , and J. P. , Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault M odels, International Workshop on Logic Synthesis (IWLS), pp.59-64, 2003.

S. Krishnasw-amy, G. F. Viamontes, I. L. , and J. P. , A ccurate Reliability Evaluation and Enhancement via Probabilistic Transfer M atrices, Proc. Design Automation and Test in Europe(DATE, pp.282-287, 2005.

T. Larrabee, Test Pattern Generation Using Boolean Satisfi ability, IEEE Transactions on Computer-Aided Design, pp.4-15, 1992.
DOI : 10.1109/43.108614

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.226.6563

D. T. Franco, M. C. Vasconcelos, L. , and J. , Signal probability for reliability evaluation of logic circuits, Microelectronics Reliability, vol.48, issue.8-9, pp.1586-1591, 2008.
DOI : 10.1016/j.microrel.2008.07.002

D. Franco, M. Vasconcelos, L. , and J. , Reliability of Logic Circuits Under M ultiple Simultaneous Faults, Circuits and Systems, 2008. M WSCAS 2008. 51st M idwest Symposium on, pp.265-268, 2008.

B. Krishnamurthy and I. Tollis, Improved techniques for estimating signal probabilities, IEEE Transactions on Computers, vol.38, issue.7, pp.1041-1045, 1989.
DOI : 10.1109/12.30854

J. , H. Chen, E. Boykin, and J. A. Fortes, Reliability evaluation of logic circuits using probabilistic gate models, M icroelectronics Reliability, vol.51, pp.468-476, 2011.

J. T. Flaquer, J. Daveau, L. , and P. Roche, Fast reliability analysis of combinatorial logic circuits using conditional probabilities, ¡ce:title¿21st European Symposium on the Reliability of Electron Devices, Failure Physics and A nalysis¡/ ce:title¿. [Online]. Available, pp.1215-1218, 2010.
DOI : 10.1016/j.microrel.2010.07.058

A. A. Bdollahi, Probabilistic decision diagrams for exact probabilistic analysis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp.266-272, 2007.

E. C. , L. A. De-barros, N. , and J. , A n Effi cient Tool for Reliability Improvement Based on TM R, M icroelectronics Reliability, vol.50, issue.9 11, pp.1247-1250, 2010.

S. N. Pagliarini, L. A. , and J. , Selective H ardening M ethodology for Combinational Logic, Test Workshop (LATW), 2012.

S. N. Pagliarini, L. A. , and J. , Tow ards the M itigation of M ultiple Faults Induced by Single Event Effects: Combining Global TM R and Selective H ardening, Radiation and Its Effects on Components and Systems (RADECS), 13th European Conferenceon, 2012.

F. A. Lmeida, F. L. Kastensmidt, S. N. Pagliarini, L. Entrena, A. Lindoso et al., Single-Event-Induced Charge Sharing Effects in TM R w ith Different Levels of Granularity, Radiation and Its Effects on Components and Systems (RADECS), 13th European Conferenceon, 2012.

S. N. Pagliarini, L. A. De, B. , and J. , Selective H ardening A gainst M ultiple Faults Employing a N et-based Reliability A nalysis, Northeast Workshop on Circuits and Systems (NEWCAS). International IEEE, 2013.

L. Entrena, A. Lindoso, M. Valderas, M. Portela, and C. Ongil, Analysis of SET Effects in a PIC Microprocessor for Selective Hardening, IEEE Transactions on Nuclear Science, vol.58, issue.3, pp.1078-1085, 2011.
DOI : 10.1109/TNS.2010.2096433

L. A. De, B. , J. , T. Ban, and G. S. Gutemberg, Reliability A nalysis Based on Signifi cance, Argentine School of M icro-Nanoelectronics Technology and Applications (EAM TA), aug, pp.1-7, 2011.

I. Polian, S. Reddy, and B. Becker, Scalable Calculation of Logical M asking Effects for Selective H ardening A gainst Soft Errors, Symposium on VLSI (ISVLSI). IEEE Computer Society Annual, pp.257-262, 2008.

Q. Zhou and K. M. Ohanram, Cost-effective Radiation H ardening Technique for Combinational Logic, Computer Aided Design (ICCAD, pp.100-106, 2004.

D. Limbrick, D. Black, K. Dick, N. Tkinson, N. Gaspard et al., Impact of Logic Synthesis on Soft Error Vulnerability Using a 90-nm Bulk CM OS Digital Cell Library, Southeastcon, 2011 Proceedings of IEEE, pp.430-434, 2011.

F. De-lima-kastensmidt, G. Euberger, R. Entschke, L. Carro, and R. Reis, Designing fault-tolerant techniques for SRAM-based FPGAs, IEEE Design and Test of Computers, vol.21, issue.6, pp.552-562, 2004.
DOI : 10.1109/MDT.2004.85

R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, and R. Koga, Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits, IEEE Transactions on Nuclear Science, vol.41, issue.6, pp.2229-2234, 1994.
DOI : 10.1109/23.340567

T. Calin, M. , and R. Velazco, Upset hardened memory design for submicron CMOS technology, IEEE Transactions on Nuclear Science, vol.43, issue.6, pp.2874-2878, 1996.
DOI : 10.1109/23.556880

URL : https://hal.archives-ouvertes.fr/hal-01412461

M. Ghahroodi, M. Zw, and E. Ozer, Radiation hardening by design: A novel gate level approach, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp.74-79, 2011.
DOI : 10.1109/AHS.2011.5963919

K. Parker and E. M. Ccluskey, Probabilistic Treatment of General Combinational N etw orks, IEEE Transactions, vol.24, issue.6, pp.668-670, 1975.

S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, Estimate of Signal Probability in Combinational Logic N etw orks, European Test Conference Proceedings of the1st, pp.132-138, 1989.

S. Pagliarini, L. De, B. , and J. , SN aP: a N ovel H ybrid M ethod for Circuit Reliability A ssessment Under M ultiple Faults, European Symposium on theReliability of Electron Devices, FailurePhysics and Analysis, 2013.

S. Pagliarini, A. B. Dhia, L. De, B. , and J. , SN aP: a N ovel H ybrid M ethod for Circuit Reliability A ssessment Under M ultiple Faults, M icroelectronics Reliability, 2013.

I. Polian and J. , Selective Hardening: Toward Cost-Effective Error Tolerance, IEEE Design & Test of Computers, vol.28, issue.3, pp.54-63, 2011.
DOI : 10.1109/MDT.2010.120

C. Zoellin, H. Wunderlich, I. Polian, and B. Becker, Selective H ardening in Early Design Steps, Test Symposium (ETS), 13th European, pp.185-190, 2008.

A. Synopsys and . Department, SA ED 90nm Generic Library

F. Brglez and H. Fujiw-ara, A N eutral N etlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran, Proceedings of the International Symposium on Circuits and Systems, pp.663-698, 1985.

H. M. Urata, K. Fujiyoshi, S. , and Y. Kajitani, VLSI M odule Placement Based on Rectangle-packing by the Sequence-pair Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.15, issue.12, pp.1518-1524, 1996.

O. A. Musan, A. F. Witulski, L. W. , B. L. Bhuva, P. R. Fleming et al., Charge Collection and Charge Sharing in a 130 nm CM OS Technology, Nuclear Science IEEE Transactions on, vol.53, issue.6, pp.3253-3258, 2006.

O. A. Musan, M. Casey, B. Bhuva, D. Cm-orrow, M. Gadlage et al., Laser Verifi cation of Charge Sharing in a 90 nm Bulk CM OS Process, Nuclear Science IEEE Transactions on, vol.56, issue.6, pp.3065-3070, 2009.

N. M. Tkinson, Single-event Characterization of a 90-nm bulk CM OS digital cell library, 2010.

T. Ban and L. , Progressive module redundancy for fault-tolerant designs in nanoelectronics, Microelectronics Reliability, vol.51, issue.9-11, pp.1489-1492, 2011.
DOI : 10.1016/j.microrel.2011.06.020

URL : https://hal.archives-ouvertes.fr/hal-00637634

S. Pagliarini, G. Santos, L. De, B. , and J. , Exploring the Feasibility of Selective H ardening for Combinational Logic, European Symposium on theReliability of Electron Devices, FailurePhysics and Analysis, 2012.

S. Pagliarini, A. B. Dhia, L. , and J. , A utomatic Selective H ardening A gainst Soft Errors: A Cost-based and Regularity-aw are A pproach, Electronics, Circuits and Systems (ICECS) 19th IEEE International Conferenceon, pp.753-756, 2012.

N. A. Tkinson, A. Witulski, W. H-olman, J. Hlbin, B. Bhuva et al., Layout Technique for Single-Event Transient Mitigation via Pulse Quenching, IEEE Transactions on Nuclear Science, vol.58, issue.3, pp.885-890, 2011.
DOI : 10.1109/TNS.2010.2097278

R. , Y. Itsuyama, M. , and T. Onoye, N eutron Induced Single Event M ultiple Transients With Voltage Scaling and Body Biasing, Reliability Physics Symposium (IRPS), pp.3-4, 2011.

J. Black, A. Sternberg, M. A. Lles, A. Witulski, B. Bhuva et al., HBD layout isolation techniques for multiple node charge collection mitigation, IEEE Transactions on Nuclear Science, vol.52, issue.6, pp.2536-2541, 2005.
DOI : 10.1109/TNS.2005.860718

L. Entrena, A. Lindoso, E. S. Illan, S. Pagliarini, F. et al., Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects, IEEE Transactions on Nuclear Science, vol.59, issue.4, pp.811-817, 2012.
DOI : 10.1109/TNS.2012.2191796