Fiabilisation et test des processeurs dans un contexte embarqué

Abstract : Slack-time reduction is a way to improve the performance of synchronous sequential circuits. In the presence of circuit wear-out, supply voltage fluctuations and temperature variations, aggressive slack-time reduction can be achieved based on adaptive voltage and frequency scaling with feedback from in-situ slack-time monitoring. The first contribution of this work consist of a new shadow-scan solution which facilitates the implementation of faster scan Flip-Flops (FFs), enables in-situ slack-time monitoring and can be transparently handled by commercial tools for automated scan stitching and automated test pattern generation. A natural approach is to place in-situ slack-time monitors close to all sequential elements with incoming timing-critical paths or susceptible to become timing-critical due to wear-out or manufacturing variability. In latency-constrained circuits with large ratios of timing-critical paths, this methodology may result in large area overheads and minor power improvements. The second contribution of this work is an evaluation methodology of the monitoring quality delivered by a set of FFs. This methodology estimates monitor activation probabilities based on which two evaluation metrics are provided. On one hand, the expected ratio of clock cycles with at least one monitor activated can be used to estimate the temporal coverage of the in-situ slack-time monitoring scheme. On the other hand, the expected number of activated monitors per clock cycle can be used to evaluate the spatial coverage of the monitoring scheme. Finally, based on these metrics, it is shown that the monitoring quality can be significantly improved if the size of the detection window of each in-situ slack-time monitor is correlated to the slack-time of the monitored timing-critical paths.
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https://pastel.archives-ouvertes.fr/tel-01218218
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Submitted on : Tuesday, October 20, 2015 - 6:02:06 PM
Last modification on : Thursday, October 17, 2019 - 12:36:09 PM

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  • HAL Id : tel-01218218, version 1

Citation

Sébastien Sarrazin. Fiabilisation et test des processeurs dans un contexte embarqué. Electronique. Télécom ParisTech, 2015. Français. ⟨NNT : 2015ENST0015⟩. ⟨tel-01218218⟩

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