A. Sultania, D. Sylvester, and S. Sapatnekar, Transistor and pin reordering for gate oxide leakage reduction in dual T /sub ox/ circuits, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., pp.228-233, 2004.
DOI : 10.1109/ICCD.2004.1347927

R. Landauer, Irreversibility and Heat Generation in the Computing Process, IBM Journal of Research and Development, vol.5, issue.3, pp.183-191, 1961.
DOI : 10.1147/rd.53.0183

C. Bennett, Logical Reversibility of Computation, IBM Journal of Research and Development, vol.17, issue.6, pp.525-532, 1973.
DOI : 10.1147/rd.176.0525

S. Younis, Asymptotically zero energy computing using split-level charge recovery logic, 1994.

E. Fredkin and T. Toffoli, Conservative logic, International Journal of Theoretical Physics, vol.43, issue.3-4, pp.219-253, 1982.
DOI : 10.1007/BF01857727

P. Matherat, Où en est-on de la dissipation du calcul? retour à bennett, Annals of Telecommunications, vol.62, issue.5, pp.690-713, 2007.

W. Porod, R. Grondin, D. Ferry, and G. Porod, Dissipation in Computation, Physical Review Letters, vol.52, issue.3, pp.232-235, 1984.
DOI : 10.1103/PhysRevLett.52.232

D. Vasudevan, P. Lala, J. Di, and J. Parkerson, Reversible-logic design with online testability Instrumentation and Measurement, IEEE Transactions on, vol.55, issue.2, pp.406-414, 2006.

T. Hisakado, H. Iketo, and K. Okumura, Logically reversible arithmetic circuit using pass-transistor, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004.
DOI : 10.1109/ISCAS.2004.1329406

M. Pedram, Power simulation and estimation in vlsi circuits, The VLSI handbook, pp.18-27, 1999.

H. Veendrick, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits Solid-State Circuits, IEEE Journal, vol.19, issue.4, pp.468-473, 2002.

Y. I. Ismail, E. G. Friedman, and J. L. Neves, Dynamic and short-circuit power of cmos gates driving lossless transmission lines Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol.46, issue.8, pp.950-961, 1999.

W. Liu, Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey, IMM Report, 2007.

X. Qi, S. Lo, A. Gyure, Y. Luo, M. Shahram et al., Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries, Circuits and Devices Magazine, pp.39-47, 2006.
DOI : 10.1109/MCD.2006.272999

S. Mohanty, N. Ranganathan, E. Kougianos, and P. Patra, Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, 2008.

C. Piguet, Low-power electronics design, CRC, vol.17, 2005.

F. Najm, A survey of power estimation techniques in vlsi circuits Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.2, issue.4, pp.446-455, 1994.

D. Marculescu, R. Marculescu, and M. Pedram, Information theoretic measures for power analysis [logic design] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.15, issue.6, pp.599-610, 1996.

K. Muller-glaser, K. Kirsch, and K. Neusinger, Estimating essential design characteristics to support project planning for asic design management ICCAD-91, Computer-Aided Design IEEE International Conference on, pp.148-151, 1991.

P. Landman and J. Rabaey, Activity-sensitive architectural power analysis for the control path, Proceedings of the 1995 international symposium on Low power design , ISLPED '95, pp.93-98, 1995.
DOI : 10.1145/224081.224098

S. Kang, Accurate simulation of power dissipation in vlsi circuits Solid-State Circuits, IEEE Journal, vol.21, issue.5, pp.889-891, 1986.

S. Devadas and S. Malik, A survey of optimization techniques targeting low power VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, 1995.
DOI : 10.1145/217474.217536

J. Kao, M. Miyazaki, and P. Chandrakasan, A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture, IEEE Journal of Solid-State Circuits, vol.37, issue.11, 2002.
DOI : 10.1109/JSSC.2002.803957

D. Soudris, Circuits Techniques for Dynamic Power Reduction, 2005.

K. Usami and M. Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design , ISLPED '95, pp.3-8, 1995.
DOI : 10.1145/224081.224083

M. Borah, R. M. Owens, and M. J. Irwin, Transistor sizing for low power cmos circuits Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.15, issue.6, pp.665-671, 1996.

R. Hossain, M. Zheng, and A. Albicki, Reducing power dissipation in serially connected MOSFET circuits via transistor reordering, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.614-617, 1994.
DOI : 10.1109/ICCD.1994.331989

E. Musoll and J. Cortadella, Optimizing CMOS circuits for low power using transistor reordering, Proceedings ED&TC European Design and Test Conference, p.219, 1996.
DOI : 10.1109/EDTC.1996.494152

A. A. Hossain and M. Zheng, Reducing power dissipation in CMOS circuits by signal probability based transistor reordering, IEEE Transactions on Computer-Aided Design of integrated Circuits And Systems, 1996.
DOI : 10.1109/43.489107

M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low power methodology manual: for system-on-chip design, 2007.

S. Devadas, J. Carlos, J. Monteiro, and A. Monteiro, A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits, 1996.

K. Yeo and K. Roy, Low voltage, low power VLSI subsystems, 2005.

L. Wei, Z. Chen, K. Roy, M. Johnson, Y. Ye et al., Design and optimization of dual-threshold circuits for low-voltage low-power applications Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.7, issue.1, pp.16-24, 2002.

Y. Lu and V. Agrawal, Leakage and dynamic glitch power minimization using integer linear programming for v th assignment and path balancing Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, pp.909-909, 2005.

P. Pant, R. Roy, and A. Chattejee, Dual-threshold voltage assignment with transistor sizing for low power cmos circuits Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.9, issue.2, pp.390-394, 2001.

S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu et al., 1-v power supply high-speed digital circuit technology with multithreshold-voltage cmos Solid-State Circuits, IEEE Journal, vol.30, issue.8, pp.847-854, 1995.

I. Group, Itrs report on system drivers, 2007.

T. Raja, V. Agrawal, and M. Bushnell, Variable input delay cmos logic for low power design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1534-1545, 2009.

M. Hashimoto, H. Onodera, and K. Tamaru, A power optimization method considering glitch reduction by gate sizing, Proceedings of the 1998 international symposium on Low power electronics and design , ISLPED '98, pp.221-226, 1998.
DOI : 10.1145/280756.280907

S. Kim, J. Kim, and S. Hwang, New path balancing algorithm for glitch power reduction, Circuits, Devices and Systems, IEE Proceedings, pp.151-156, 2001.
DOI : 10.1049/ip-cds:20010343

V. Agrawal, M. Bushnell, G. Parthasarathy, and R. Ramadoss, Digital circuit design for minimum transient energy and a linear programming method, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), pp.434-439, 1999.
DOI : 10.1109/ICVD.1999.745194

H. Lee, H. Shin, and J. Kim, Glitch elimination by gate freezing, gate sizing and buffer insertion for low power optimization circuit, Proceedings of the 30th Annual Conference of IEEE Industrial Electronics Society, IECON, pp.2126-2131, 2004.

O. Coudert, Gate sizing for constrained delay/power/area optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.465-472, 1997.
DOI : 10.1109/92.645073

L. Wang, M. Olbrich, E. Barke, T. Buchner, M. Buhler et al., A gate sizing method for glitch power reduction, 2011 IEEE International SOC Conference, pp.24-29, 2011.
DOI : 10.1109/SOCC.2011.6085070

Y. Lu and V. Agrawal, CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff, Journal of Low Power Electronics, vol.2, issue.3, pp.378-387, 2006.
DOI : 10.1166/jolpe.2006.100

M. Ketkar and S. Sapatnekar, Standby power optimization via transistor sizing and dual threshold voltage assignment, IEEE/ACM International Conference on Computer Aided Design, ICCAD, pp.375-378, 2002.

Y. Lu and V. Agrawal, CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff, Journal of Low Power Electronics, vol.2, issue.3, pp.378-387, 2006.
DOI : 10.1166/jolpe.2006.100

E. Vittoz, Weak inversion for ultimate low-power logic, Low-Power CMOS Circuits, 2006.

Y. Tsividis and C. Mcandrew, Operation and Modeling of the MOS Transistor, 1999.

D. Markovic, C. Wang, L. Alarcon, and J. Rabaey, Ultralow-Power Design in Near-Threshold Region, Proceedings of the IEEE, vol.98, issue.2, pp.237-252, 2010.
DOI : 10.1109/JPROC.2009.2035453

A. Wang and A. Chandrakasan, A 180-mV subthreshold FFT processor using a minimum energy design methodology Solid-State Circuits, IEEE Journal, vol.40, issue.1, pp.310-319, 2004.

S. Hanson, B. Zhai, D. Blaauw, D. Sylvester, A. Bryant et al., Energy optimality and variability in subthreshold design, Proceedings of the 2006 international symposium on Low power electronics and design , ISLPED '06, pp.363-365, 2006.
DOI : 10.1145/1165573.1165660

J. Kwong and A. Chandrakasan, Variation-driven device sizing for minimum energy sub-threshold circuits, Proceedings of the 2006 international symposium on Low power electronics and design , ISLPED '06, pp.8-13, 2006.
DOI : 10.1145/1165573.1165578

D. Bol, D. Kamel, D. Flandre, and J. Legat, Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic, Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, ISLPED '09, pp.3-8, 2009.
DOI : 10.1145/1594233.1594237

D. Bol, R. Ambroise, D. Flandre, and J. Legat, Interests and limitations of technology scaling for subthreshold logic Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.17, issue.10, pp.1508-1519, 2009.

D. Bol, Pushing ultra-low-power digital circuits into the nanometer era, 2008.

A. Wang, A. Chandrakasan, and S. Kosonocky, Optimal supply and threshold scaling for subthreshold CMOS circuits, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, pp.5-9, 2002.
DOI : 10.1109/ISVLSI.2002.1016866

B. Calhoun, A. Wang, and A. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits Solid-State Circuits, IEEE Journal, vol.40, issue.9, pp.1778-1786, 2005.

C. Kim, H. Soeleman, and K. Roy, Ultra-low-power dlms adaptive filter for hearing aid applications Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.11, issue.6, pp.1058-1067, 2003.

H. Soeleman, K. Roy, and B. Paul, Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic, VLSI Design 2001. Fourteenth International Conference on VLSI Design, pp.211-214, 2001.
DOI : 10.1109/ICVD.2001.902662

D. Bol, J. De-vos, C. Hocquet, F. Botman, F. Durvaux et al., A 25mhz 7µw/mhz ultra-low-voltage microcontroller soc in 65nm lp/gp cmos for low-carbon wireless sensor nodes, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp.490-492, 2012.

M. Seok, D. Jeon, C. Chakrabarti, D. Blaauw, and D. Sylvester, A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining, 2011 IEEE International Solid-State Circuits Conference, pp.342-344, 2011.
DOI : 10.1109/ISSCC.2011.5746346
URL : https://hal.archives-ouvertes.fr/hal-00922494

J. Kwong, Y. Ramadass, N. Verma, M. Koesler, K. Huber et al., A 65nm sub-v t , microcontroller with integrated sram and switchedcapacitor dc-dc converter, Solid-State Circuits Conference Digest of Technical Papers. IEEE International, pp.318-616, 2008.

T. Kim, J. Liu, J. Keane, and C. Kim, A 0.2 v, 480 kb subthreshold sram with 1 k cells per bitline for ultra-low-voltage computing Solid-State Circuits, IEEE Journal, vol.43, issue.2, pp.518-529, 2008.
URL : https://hal.archives-ouvertes.fr/in2p3-00011479

M. Seok, S. Hanson, Y. Lin, Z. Foo, D. Kim et al., The phoenix processor: A 30pw platform for sensor applications, VLSI Circuits IEEE Symposium on, pp.188-189, 2008.

D. Boning and S. Nassif, Models of process variations in device and interconnect Design of high performance microprocessor circuits, 2000.

J. Kao, M. Miyazaki, and A. Chandrakasan, A 175-mv multiply-accumulate unit using an adaptive supply voltage and body bias architecture Solid-State Circuits, IEEE Journal, vol.37, issue.11, pp.1545-1554, 2002.

M. Pelgrom, A. Duinmaijer, and A. Welbers, Matching properties of mos transistors Solid-State Circuits, IEEE Journal, vol.24, issue.5, pp.1433-1439, 1989.

P. Jespers, The Gm/ID Methodology, a Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches, 2009.
DOI : 10.1007/978-0-387-47101-3

H. Thode, Testing for normality, CRC, vol.164, 2002.
DOI : 10.1201/9780203910894

N. Beaulieu, A. Abu-dayya, and P. Mclane, Comparison of methods of computing lognormal sum distributions and outages for digital wireless applicationsServing Humanity Through Communications, ICC'94, SUPERCOMM/ICC'94IEEE International Conference on, pp.1270-1275, 1994.

N. Faouzi and M. Maurin, Sur la loi de la somme de variables log-normales: application à la fiabilité de temps de parcours routiers, tech. rep, 2006.

B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, Analysis and mitigation of variability in subthreshold design, Proceedings of the 2005 international symposium on Low power electronics and design , ISLPED '05, pp.20-25, 2005.
DOI : 10.1145/1077603.1077610

B. Calhoun and A. Chandrakasan, Characterizing and modeling minimum energy operation for subthreshold circuits, Proceedings of the 2004 international symposium on Low power electronics and design , ISLPED '04, 2004.
DOI : 10.1145/1013235.1013265

M. Seok, S. Hanson, D. Sylvester, and D. Blaauw, Analysis and optimization of sleep modes in subthreshold circuit design, Proceedings of the 44th annual Design Automation Conference, pp.694-699, 2007.

M. Slimani and P. Matherat, Analyse d'architectures de multiplieurs en vue de la basse consommation, Journées Nationales du Réseau Doctoral en Microélectronique, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00491095

M. Slimani and P. Matherat, Multiple threshold voltage for glitch power reduction, 2011 Faible Tension Faible Consommation (FTFC), pp.67-70, 2011.
DOI : 10.1109/FTFC.2011.5948921
URL : https://hal.archives-ouvertes.fr/hal-00598877

M. Slimani, F. Silveira, and P. Matherat, Variability-Speed-Consumption Trade-off in Near Threshold Operation, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, pp.308-316, 2011.
DOI : 10.1109/JPROC.2009.2035453
URL : https://hal.archives-ouvertes.fr/hal-00629297

M. Slimani, P. Matherat, and Y. Mathieu, A dual threshold voltage technique for glitch minimization, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012.
DOI : 10.1109/ICECS.2012.6463554
URL : https://hal.archives-ouvertes.fr/hal-01166345

B. Calhoun, Low energy digital circuit design using sub-threshold operation, 2005.