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Maîtrise de la couche hyperviseur sur les architectures multi-coeurs COTS dans un contexte avionique

Abstract : We focus in this thesis on issues related to COTS multi-core processors mastering, especially regarding hard real-time constraints, in order to enable their usage in future avionics equipment. We aim at applying existing Worst Case Execution Time (WCET) evaluation methods on a set of tasks similar to those we can find in avionics software. At runtime, tasks executed among different cores are likely to access hardware resources at the same time, e.g. the main memory. It may lead to additional delays due to hardware contention, called “interferences”. Interferences slow down embedded software within ranges that may be important. Additionnally, no bound has been established for their impact on WCET when using COTS processors, that target larger markets than avionics. We try to provide guarantees that all interferences are eliminated through software, as COTS processors do not provide adequate mechanisms at hardware level. We extend deterministic software concepts that have been developed in the state of the art, in order to make them compliant with the use of legacy software. We introduce the concept of "control software", which is functionnaly neutral, is replicated among all cores, and performs active control of core's accesses to shared resources, so that concurrent accesses are temporally isolated. We formalize and study in this thesis the problem of control software feasibility on COTS processors, and questions of efficiency with regard to legacy avionics software.
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Submitted on : Monday, July 4, 2016 - 5:09:19 PM
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  • HAL Id : tel-01341758, version 1


Xavier Jean. Maîtrise de la couche hyperviseur sur les architectures multi-coeurs COTS dans un contexte avionique. Génie logiciel [cs.SE]. Télécom ParisTech, 2015. Français. ⟨NNT : 2015ENST0034⟩. ⟨tel-01341758⟩



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