Reliability analysis of spintronic device based logic and memory circuits

Abstract : Spin transfer torque magnetic tunnel junction (STT-MTJ) has been considered as a promising candidate for next generation of non-volatile memories and logic circuits, because it provides a perfect solution to overcome the bottleneck of increasing static power caused by CMOS technology scaling. However, its commercialization is limited by the poor reliability, which deteriorates severely with device scaling down. This thesis focuses on the reliability investigation of MTJ based non-volatile circuits. Firstly, a compact model of MTJ including main reliability issues is proposed and validated by the comparison with experimental data. Based on this accurate model, the reliability of typical circuits is analyzed and reliability optimization methodology is proposed. Finally, the stochastic switching behavior is utilized in some new designs of conventional applications.
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  • HAL Id : tel-01743849, version 1

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You Wang. Reliability analysis of spintronic device based logic and memory circuits. Electronics. Télécom ParisTech, 2017. English. ⟨NNT : 2017ENST0005⟩. ⟨tel-01743849⟩

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