F. B. Armelin, L. A. Naviner, R. ;-d'amore, and I. A. Azevedo, Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation, IEEE International Conference on Electronics, Circuits and Systems (ICECS). Proceedings, pp.277-280, 2016.

G. Asadi and M. Tahoori, An Accurate SER Estimation Method Based on Propagation Probability, Design, Automation and Test in Europe. Proceedings... Munich: IEEE, pp.306-307, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00181534

J. Baraza, J. Gracia, D. Gil, and P. Gil, A prototype of a VHDL-based fault injection tool: description and application, Journal of Systems Architecture, issue.10, pp.847-867, 2002.

J. Baraza, J. Gracia, D. Gil, and P. Gil, Improvement of fault injection techniques based on VHDL code modification, 10th IEEE International High-Level Design Validation and Test Workshop. Proceedings... Napa Valley: IEEE, pp.19-26, 2005.

H. J. Barnaby, Total-Ionizing-Dose Effects in Modern CMOS Technologies, IEEE Transactions on Nuclear Science, issue.6, pp.3103-3121, 2006.

L. Berrojo, I. Gonzalez, F. ;. Corno, M. Sonza-reorda, G. Squillero et al., New techniques for speeding-up fault-injection campaigns, Design, Automation and Test in Europe. Proceedings, pp.847-852, 2002.

D. Binder, E. C. Smith, A. B. Holman, C. Bottoni, B. Coeffic et al., Partial triplication of a SPARC-V8 microprocessor using fault injection, 6th IEEE Latin American Symposium on Circuits & Systems (LASCAS). Proceedings, pp.2675-2680, 1975.

. Montevideo, , pp.1-4, 2015.

C. Bottoni, M. Glorieux, J. Daveau, G. Gasiot, F. Abouzeid et al., Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor, IEEE International Reliability Physics Symposium. Proceedings... Waikoloa: IEEE, pp.1-6, 2014.
URL : https://hal.archives-ouvertes.fr/hal-02412075

J. Boudenot, R. Velazco, P. Fouillat, and R. Reis, Radiation Effects on Embedded Systems, pp.1-9, 2007.

J. Boue, P. Petillon, and Y. Crouzet, MEFISTO-L: a VHDL-based fault injection tool for the experimental assessment of fault tolerance, 28th Annual International Symposium on Fault-Tolerant Computing. Proceedings

. Munich, , pp.168-173, 1998.

N. Buard and L. Anghel, Soft Errors in Modern Electronic Systems, vol.4, pp.77-102, 2011.

B. S. Goda, R. P. Kraft, S. R. Carlough, T. W. Krawczyk, and J. F. Mcdonald, Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs, Field-Programmable Logic and Applications, pp.59-69, 2001.

J. Han, H. Chen, E. Boykin, and J. Fortes, Reliability evaluation of logic circuits using probabilistic gate models. Microelectronics Reliability, pp.468-476, 2011.

J. Han, H. Chen, J. Liang, P. Zhu, Z. Yang et al., A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation, IEEE Transactions on Computers, issue.6, pp.1336-1350, 2014.

P. Hinrichsen, A. Houdayer, A. Barry, and J. Vincent, Proton induced damage in SiC light emitting diodes, IEEE Transactions on Nuclear Science, issue.6, pp.2808-2812, 1998.

A. Holmes-siedle and L. Adams, Handbook of radiation effects, vol.642, 2002.

. Institute and . Electronics-engineers, 1149.1-1990 -IEEE Standard Test Access Port and Boundary-Scan Architecture, vol.139, 1993.

. Institute and . Electronics-engineers, 1364-1995 -IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, vol.676, 1996.

. Intel, Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide, vol.18, 2018.

. Intel and . Agilex, Logic Array Blocks and Adaptive Logic Modules User Guide, vol.20, 2019.

E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, Fault injection into VHDL models: the MEFISTO tool, 24th IEEE International Symposium on Fault-Tolerant Computing. Proceedings, pp.66-75, 1994.

Y. S. Jeong, S. M. Lee, and S. E. Lee, A Survey of Fault-Injection Methodologies for Soft Error Rate Modeling in Systems-on-Chips, Bulletin of Electrical Engineering and Informatics, issue.2, pp.169-177, 2016.

G. Kanawati, N. Kanawati, and J. Abraham, FERRARI: a tool for the validation of system dependability properties, 22nd International Symposium on Fault-Tolerant Computing. Proceedings... Boston: IEEE, pp.336-344, 1992.

J. Karlsson, P. Liden, P. Dahlgren, R. Johansson, and U. Gunneflo, Using heavy-ion radiation to validate fault-handling mechanisms, IEEE Micro, issue.1, pp.8-23, 1994.

R. Koga, S. Pinkerton, S. Moss, D. Mayer, S. Lalumondiere et al., Observation of single event upsets in analog microcircuits, IEEE Transactions on Nuclear Science, issue.6, pp.1838-1844, 1993.

M. Kooli and G. Di-natale, A survey on simulation-based fault injection tools for complex systems, 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Proceedings
URL : https://hal.archives-ouvertes.fr/hal-01075473

, LATTICE SEMICONDUCTOR. iCE40 UltraPlus Family. Portland, vol.51, 2018.

R. Leveugle and K. Hadjiat, Optimized generation of VHDL mutants for injection of transition errors, 13th Symposium on Integrated Circuits and Systems Design. Proceedings... Manaus, pp.243-248, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00015067

. Lopes, A. Filho, and R. D'amore, Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation. IET Computers & Digital Techniques, pp.160-165, 2012.

C. Lopez-ongil, M. Garcia-valderas, M. Portela-garcia, and L. Entrena, Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation, IEEE Transactions on Nuclear Science, issue.1, pp.252-261, 2007.

H. Madeira, M. Rela, F. Moreira, and J. G. Silva, RIFLE: A general purpose pin-level fault injector

, Dependable Computing -EDCC-1, vol.12, pp.197-216, 1994.

M. Integrated, Application Note 4400 -Pseudo Random Number Generation Using Linear Feedback Shift Registers, vol.7, 2010.

D. May and W. Stechele, An FPGA-based probability-aware fault simulator, International Conference on Embedded Computer Systems (SAMOS)

.. .. Proceedings and . Samos, , pp.302-309, 2012.

D. May and W. Stechele, A resource-efficient probabilistic fault simulator, 23rd International Conference on Field programmable Logic and Applications. Proceedings... Porto: IEEE, pp.1-4, 2013.

. Microsemi and . Igloo, SmartFusion and Fusion Macro Library Guide for Software v10.1. Aliso Viejo, vol.180, 2010.

. Microsemi.-proasic3e, FPGA Fabric User's Guide. Rev. 4. Aliso Viejo, vol.348, 2012.

. Microsemi, ProASIC3/E Starter Kit User's Guide. Aliso Viejo, vol.54, 2012.

. Microsemi, ProASIC3E Flash Family FPGAs with Optional Soft ARM Support. Rev. 15. Aliso Viejo, vol.160, 2015.

A. Mohammadi, M. Ebrahimi, A. Ejlali, and S. G. Miremadi, SCFIT: A FPGA-based fault injection technique for SEU fault model, Design, Automation & Test in Europe Conference & Exhibition (DATE). Proceedings... Dresden: IEEE, pp.586-589, 2012.

R. Natella, D. Cotroneo, and H. S. Madeira, Assessing Dependability with Software Fault Injection, ACM Computing Surveys, issue.3, pp.1-55, 2016.

L. A. Naviner, J. F. Naviner, G. G. Santos-jr, and . Dos,

E. C. Marques and N. M. Paiva-jr, FIFA: A fault-injectionâfault-analysis-based tool for reliability assessment at RTL level. Microelectronics Reliability, pp.1459-1463, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00627134

F. Nichitiu, J. R. Drummond, J. Zou, and R. Deschambault, Solar particle events seen by the MOPITT instrument, Journal of Atmospheric and Solar-Terrestrial Physics, vol.18, pp.1797-1803, 2004.

E. Okuno, E. M. Yoshimura, . Física-das-radiações, and . Sao-paulo, , vol.296, 2010.

. Osvvm and . Org, Open Source VHDL Verification Methodology, 2018.

B. Parrotta, M. ;. Rebaudengo, M. Sonza-reorda, and M. Violante, New techniques for accelerating fault injection in VHDL descriptions, 6th IEEE International On-Line Testing Workshop. Proceedings... Palma de Mallorca, pp.61-66, 2000.

E. C. Pereira-junior, Desenvolvimento de uma plataforma para ensaios de efeitos da radiação ionizante em memórias, 2015.

J. C. Pickel and J. T. Blandford, Cosmic Ray Induced in MOS Memory Cells, IEEE Transactions on Nuclear Science, issue.6, pp.1166-1171, 1978.

M. Portela-garcia, C. Lopez-ongil, M. Garcia-valderas, and L. Entrena, A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors, 13th IEEE International On-Line Testing Symposium (IOLTS). Proceedings... Crete: IEEE, pp.101-106, 2007.

M. Raji, H. Pedram, and B. Ghavami, A practical metric for soft error vulnerability analysis of combinational circuits. Microelectronics Reliability, vol.55, pp.448-460, 2015.

G. Reitz, Characteristic of the radiation field in low earth orbit and in deep space, Zeitschrift für Medizinische Physik, vol.4, pp.233-243, 2008.

S. Rezaei, S. G. Miremadi, H. Asadi, and M. Fazeli, Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. Microelectronics Reliability, pp.1412-1420, 2014.

S. Rezgui, J. J. Wang, E. C. Tung, B. Cronquist, and J. Mccollum, New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs, IEEE Transactions on Nuclear Science, issue.6, pp.2512-2524, 2007.

F. M. Sajjade, N. K. Goyal, B. Varaprasad, and R. Moogina, Radiation Hardened by Design Latches -A Review and SEU Fault Simulations. Microelectronics Reliability, pp.127-135, 2017.

V. Sieh, O. Tschache, and F. Balbach, VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions, 27th IEEE International Symposium on Fault Tolerant Computing. Proceedings... Seattle: IEEE Comput, pp.32-36, 1997.

C. Slayman, JEDEC Standards on Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray Induced Soft Errors, pp.55-76, 2011.

E. Snow, A. Grove, and D. Fitzgerald, Effects of ionizing radiation on oxidized silicon surfaces and planar devices, Proceedings of the IEEE, pp.1168-1185, 1967.

W. Sootkaneung and K. K. Saluja, Gate input reconfiguration for combating soft errors in combinational circuits, International Conference on Dependable Systems and Networks Workshops (DSN-W). Proceedings, pp.107-112, 2010.

V. Srinivasan, A. Sternberg, A. Duncan, W. Robinson, B. Bhuva et al., Single-event mitigation in combinational logic using targeted data path hardening, IEEE Transactions on Nuclear Science, issue.6, pp.2516-2523, 2005.

J. Srour, C. Marshall, and P. Marshall, Review of displacement damage effects in silicon devices, IEEE Transactions on Nuclear Science, issue.3, pp.653-670, 2003.

E. Stassinopoulos and J. Raymond, The space radiation environment for electronics, Proceedings of the IEEE, pp.1423-1442, 1988.

L. Sterpone, N. Battezzati, and V. Ferlet-cavrois, Analysis of SET Propagation in Flash-Based FPGAs by Means of Electrical Pulse Injection, IEEE Transactions on Nuclear Science, v, vol.57, issue.4, pp.1820-1826, 2010.

L. A. Tambara, A. Akhmetov, D. V. Bobrovsky, and F. L. Kastensmidt, On the Characterization of Embedded Memories of Zynq-7000 All Programmable SoC under Single Event Upsets Induced by Heavy Ions and Protons, 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS). Proceedings... Moscow: IEEE, pp.1-4, 2015.

L. A. Tambara, F. L. Kastensmidt, N. H. Medina, N. Added, V. A. Aguiar et al., Heavy Ions Induced Single Event Upsets Testing of the 28 nm Xilinx Zynq-7000 All Programmable SoC, IEEE Radiation Effects Data Workshop (REDW). Proceedings

, Boston, pp.1-6, 2015.

T. Turflinger, Single-event effects in analog and mixed-signal integrated circuits, IEEE Transactions on Nuclear Science, issue.2, pp.594-602, 1996.

R. Velazco, P. Fouillat, and R. Reis, Radiation Effects on Embedded Systems, vol.269, 2007.

M. Violante, Accurate single-event-transient analysis via zero-delay logic simulation, IEEE Transactions on Nuclear Science, issue.6, pp.2113-2118, 2003.

P. C. Ward and J. R. Armstrong, Behavioral fault simulation in VHDL, 27th ACM/IEEE design automation conference -DAC'90. Proceedings, pp.587-593, 1990.

G. Wirth, F. L. Kastensmidt, and I. Ribeiro, Single Event Transients in Logic Circuits -Load and Propagation Induced Pulse Broadening, IEEE Transactions on Nuclear Science, issue.6, pp.2928-2935, 2008.

, XILINX. XC2064-XC2018 Logic Cell Array, vol.41, 1985.

. Xilinx, Spartan-3 Generation FPGA User Guide, vol.512, 2011.

S. Yang, Logic Synthesis and Optimization Benchmarks User Guide Version 3.0. North Carolina, vol.45, 1991.

H. Ziade, R. Ayoubi, and R. Velazco, Survey on Fault Injection Techniques. The International Arab Journal of Information Technology, p.81, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00105562

, The proposed approach for SET emulation covers a good range of pulse widths, from approximately 500 ps to more than 5 ns, with small pulse distortions. This range is in agreement with that presented in Rezgui et al. (2007), which were characterised by radiation tests, for the same device technology. In general, the pulse distortions caused by the Saboteurs are small

, Étape 3 consiste à simuler le DUT avec le scénario opérationnel souhaité pour générer le fichier de modification de la valeur (VCD -Value Change Dump), à partir duquel la distribution des valeurs d'entrée sont extraits. Le testbench de cette simulation doit utiliser le même Driver utilisé dans le cadre de la simulation, abordé au début de ce section

, Étape 4 consiste à extraire la distribution des valeurs d'entrée du fichier VCD, en générant un rapport avec le pourcentage de temps pendant lequel chaque CLB a été soumis à chaque valeurs d'entrée

, Étape 5 consiste à calculer les susceptibilités SET spécifiques de chaque CLB pour le scénario opérationnel, à l'aide du rapport sur la distribution des valeurs d'entrée et des informations sur les susceptibilités SET. Le résultat est un fichier de rapport avec les susceptibilités SET de chaque CLB utilisé dans le DUT. Cette étape est une modification de l'étape 3 de la version simplifiée

, Étape 6 consiste à générer le testbench utilisé dans le cadre de la simulation

, Étape 7 correspond à la simulation réelle du DUT injectant la distribution pondérée des SET, comme à l'étape 5 de la version simplifiée

, Ajout des saboteurs

, Le processus d'insertion de saboteurs dans le DUT, qui est exactement identique dans les deux versions de la stratégie, se traduit par : 1. au port de l'entité, ajouter le signal d'erreur (SET) et les signaux d'activation pour chaque CLB

, pour chaque CLB, créer un nouveau signal, qui remplace la sortie d'origine du CLB et est utilisé comme entrée des saboteurs

, connecter la sortie du CLB à ce nouveau signal ; et d'estimation SEV prenant en compte à la fois la topologie et la distribution des valeurs d'entrée utilise les susceptibilités SET obtenues comme

, Pour toutes les estimations SEV, nous avons injecté l'équivalent de 1000 SET par transistor, ce qui donne 82000 SET à l'intérieur de chaque CLB

. ·n-clb, Pour le processus à distribution uniforme, nous avons adopté la susceptibilité moyenne de toutes les configurations combinatoires de la bibliothèque

, Les estimations SEV obtenues pour chaque circuit de référence analysé sont présentées dans le Table D.1. Pour chaque référence, Table D.1 inclut la quantité de SE observées dans chaque catégorie d'estimation SEV et la SEV estimée respective

, En considérant uniquement l'effet topologique (stratégie simplifiée), l'erreur moyenne est de 4,70 %. Enfin, la prise en compte de la topologie et de l'effet de distribution des valeurs d'entrée (stratégie complète) entraîne une erreur moyenne de 0,68 %. Le calcul de ces erreurs moyennes