102 7.2 Preemption Costs for Dynamic TDM-based Arbitration ,
107 7.3.3 Scheduling with Criticality Inheritance (SHDi) ,
113 7.4.3 Results for (Preemptive) Arbitration Schemes ,
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, novel dynamic TDM-based arbitration schemes. We envisioned that the task's criticality level should not only be used by the task scheduler, but also by the memory arbiter. The arbiter associates a deadline with each memory request of a critical task, which corresponds to the end of its corresponding slot under a strict TDM scheme
Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study, 29th Euromicro Conference on Real-Time Systems (ECRTS), vol.76, p.22, 2017. ,
Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration, 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pp.3-14, 2008. ,
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems. 1st ,
Composability and Predictability for Independent Application Development,Verification, and Execution, Multiprocessor System-on-Chip: Hardware Design and Tool Integration, pp.25-56, 2011. ,
Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems, Real-Time Systems, vol.48, pp.1573-1383, 2012. ,
A Generic and Compositional Framework for Multicore Response Time Analysis, Proceedings of the International Conference on Real Time and Networks Systems. RTNS '15, pp.129-138, 2015. ,
URL : https://hal.archives-ouvertes.fr/hal-01231700
Applying new scheduling theory to static priority pre-emptive scheduling, In: Software Engineering Journal, vol.8, pp.284-292, 1993. ,
Real-Time System Scheduling, Predictably Dependable Computing Systems, pp.978-981, 1995. ,
A Time-composable Operating System, 12th International Workshop on Worst-Case Execution Time Analysis. Ed. by Tullio Vardanega, vol.23, pp.69-80, 2012. ,
Scratchpad memory: a design alternative for cache on-chip memory in embedded systems, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002, pp.73-78, 2002. ,
The partitioned multiprocessor scheduling of sporadic task systems, 26th IEEE International Real-Time Systems Symposium (RTSS'05), vol.9, 2005. ,
Response-Time Analysis for Mixed Criticality Systems, 32nd Real-Time Systems Symposium (RTSS), pp.34-43, 2011. ,
The partitioned multiprocessor scheduling of deadlineconstrained sporadic task systems, IEEE Transactions on Computers, vol.55, issue.7, 2006. ,
Dynamic-and Static-priority Scheduling of Recurring Real-time Tasks, In: Real-Time Systems, vol.24, pp.1573-1383, 2003. ,
Worst-case execution time analysis of real-time tasks executed on a multicore architecture, 2012. ,
URL : https://hal.archives-ouvertes.fr/tel-00746073
Temporal Isolation on Multiprocessing Architectures, Proceedings of the 48th Design Automation Conference. DAC '11, pp.274-279, 2011. ,
Predicting computation time for advanced processor architectures, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS, pp.89-96, 2000. ,
A Survey of Research into Mixed Criticality Systems, ACM Comput. Surv, vol.50, 2017. ,
Elastic task model for adaptive rate control, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279, pp.286-295, 1998. ,
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling, 17th IEEE Real-Time Systems Symposium, pp.264-274, 1996. ,
Scheduling Algorithms for Hard Real-Time Systems-A Brief Survey, 1987. ,
Experimental evaluation of code properties for WCET analysis, RTSS 2003. 24th IEEE Real-Time Systems Symposium, pp.190-199, 2003. ,
Independence -a misunderstood property of and for probabilistic real--time systems, Alan Burns 60th Anniversary, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00920504
The Locality Principle, Commun. ACM, vol.48, issue.7, pp.19-24, 2005. ,
Techniques For The Synthesis Of Multiprocessor Tasksets, Workshop on Analysis Tools and Methodologies for Embedded and Real-time Systems (WATERS), pp.6-11, 2010. ,
Hiérarchie mémoire : les caches, Techniques de l'ingénieur Architectures matérielles base documentaire : TIB308DUO.ref. article, p.1002, 2012. ,
Efficient and Precise Cache Behavior Prediction for Real-Time Systems, Real-Time Systems, vol.17, pp.1573-1383, 1999. ,
A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems, IEEE Trans. Comput, vol.66, issue.2, pp.18-9340, 2017. ,
MiBench: A free, commercially representative embedded benchmark suite, Proc. of the Int. Workshop on Workload Characterization, pp.3-14, 2001. ,
Towards Compositionality in Execution Time Analysis: Definition and Challenges, In: SIGBED Rev, vol.12, pp.1551-3688, 2015. ,
Statistical-Based WCET Estimation and Validation, Intl. Workshop on Worst-Case Execution Time Analysis (WCET'09), vol.10, pp.978-981, 2009. ,
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?, In: 2018 IEEE Real-Time Systems Symposium (RTSS), pp.495-505, 2018. ,
Criticality-and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.1-11, 2016. ,
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems, 21st IEEE Real-Time and Embedded Technology and Applications Symposium, pp.307-316, 2015. ,
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems, ACM Trans. Embed. Comput. Syst, vol.16, issue.4, 2017. ,
Scheduling coprocessor for enhanced least-laxity-first scheduling in hard real-time systems, Proceedings of 11th Euromicro Conference on Real-Time Systems. Euromicro RTS'99, pp.208-215, 1999. ,
Adaptive History-Based Memory Schedulers, 37th International Symposium on Microarchitecture, pp.343-354, 2004. ,
Maximizing the execution rate of lowcriticality tasks in mixed criticality systems, Proc. of the 1st Intl. Workshop on Mixed Criticality Systems (WMC), pp.43-48, 2013. ,
Finding Response Times in a Real-Time System, The Computer Journal, vol.29, 1986. ,
Cache Write Policies and Performance, vol.21, pp.191-201, 1993. ,
Static Analysis of Multi-core TDMA Resource Arbitration Delays, Real-Time Syst, vol.50, pp.922-6443, 2014. ,
Bounding memory interference delay in COTS-based multi-core systems, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.145-154, 2014. ,
Slack-based Resource Arbitration for Real-time Networkson-chip, Proceedings of the Conference on Design, Automation & Test in Europe. DATE '16. EDA, pp.978-981, 2016. ,
Flexible TDM-based Resource Management in On-chip Networks, Int. Conf. on Real Time and Networks Systems, pp.978-979, 2015. ,
Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems, Int. Conf. on Real-Time Networks and Systems, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01096102
Performance of Real-time Bus Scheduling Algorithms, Proceedings of the 1986 ACM SIGMETRICS Joint International Conference on Computer Performance Modelling, Measurement and Evaluation. SIGMETRICS '86/PERFORMANCE '86 ,
, , pp.44-53, 1986.
Generalized Tardiness Bounds for Global Multiprocessor Scheduling, 28th IEEE International Real-Time Systems Symposium (RTSS, pp.413-422, 2007. ,
Architecture and Analysis of a Dynamically-scheduled Real-time Memory Controller, Real-Time Syst, vol.52, pp.922-6443, 2016. ,
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, J. ACM, vol.20, pp.4-5411, 1973. ,
A Survey of Techniques for Designing and Managing CPU Register File, Concurrency and Computation Practice and Experience, vol.29, 2016. ,
Static Cache Simulation and Its Applications, PhD Dissertation, 1994. ,
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp.146-160, 2007. ,
Accurate Estimation of Cache-related Preemption Delay, Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. CODES+ISSS '03, pp.201-206, 2003. ,
Fair Queuing Memory Systems, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 39, pp.208-222, 2006. ,
Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions, In: ACM Trans. Embed. Comput. Syst, vol.12, pp.1539-9087, 2013. ,
Hardware Support for WCET Analysis of Hard Real-time Multicore Systems, Proceedings of the International Symposium on Computer Architecture. ISCA '09, pp.57-68, 2009. ,
A Real-time Java Chip-multiprocessor, In: ACM Trans. Embed. Comput. Syst, vol.10, issue.1, pp.1-9, 2010. ,
WCET Analysis in Shared Resources Real-time Systems with TDMA Buses, Proceedings of the 23rd International Conference on Real Time and Networks Systems. RTNS '15, pp.183-192, 2015. ,
URL : https://hal.archives-ouvertes.fr/hal-01243244
Memory access scheduling, Proceedings of 27th International Symposium on Computer Architecture, pp.128-138, 2000. ,
Bringing Theory to Practice: Predictability and Performance in Embedded Systems, pp.11-21, 2011. ,
Priority inheritance protocols: an approach to real-time synchronization, IEEE Transactions on Computers, vol.39, pp.1175-1185, 1990. ,
Real-time computing: a new discipline of computer science and engineering, Proceedings of the IEEE, vol.82, pp.18-9219, 1994. ,
, Cache Memories". In: ACM Comput. Surv, vol.14, issue.3, pp.473-530, 1982.
Deadline Scheduling for Real-Time Systems: Edf and Related Algorithms, p.792382692, 1998. ,
An Elastic Mixed-Criticality task model and its scheduling algorithm, 2013 Design, Automation Test in Europe Conference Exhibition (DATE), pp.147-152, 2013. ,
Scheduling algorithms for Elastic Mixed-Criticality tasks in multicore systems, 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, pp.352-357, 2013. ,
A Real-Time Scratchpad-Centric OS for Multi-Core Embedded Systems, Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.1-11, 2016. ,
Cache memory aware priority assignment and scheduling simulation of real-time embedded systems, 2017. ,
URL : https://hal.archives-ouvertes.fr/tel-01773862
The state explosion problem, Lectures on Petri Nets I: Basic Models: Advances in Petri Nets. Ed. by Wolfgang Reisig and Grzegorz Rozenberg, pp.429-528, 1998. ,
Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration, 1988. ,
Preemptive Scheduling of Multi-criticality Systems with Varying Degrees of Execution Time Assurance, 28th IEEE International Real-Time Systems Symposium (RTSS, pp.239-243, 2007. ,
CHAPTER 2 -Network Services and Layered Architectures". In: High-Performance Communication Networks (Second Edition). Ed. by Jean Walrand and Pravin Varaiya, pp.39-102, 2000. ,
Quantitative software engineering series. Hoboken, 2017. ,
Embedded Real-Time Operating System, 2017. ,
Determining Bounds on Execution Times, Handbook on Embedded Systems, vol.14, pp.14-23, 2005. ,
The Worst-case Execution-time Problem -Overview of Methods and Survey of Tools, ACM Trans. Embed. Comput. Syst, vol.7, issue.3, 2008. ,
Worst Case Analysis of DRAM Latency in Multirequestor Systems, Real-Time Systems Symposium (RTSS), pp.372-383, 2013. ,
Rmetrics -Modelling Extreme Events in Finance, 2017. ,
Optimizing Tunable WCET with Shared Resource Allocation and Arbitration in Hard Real-Time Multicore Systems, Real-Time Systems Symp, pp.227-238, 2011. ,
MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms, Real-Time and Embedded Technology and Applications Symposium (RTAS). 2013, pp.55-64 ,