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Robust and reliable ReRAM-based non-volatile sequential logic circuits in deeply-scaled CMOS tehnologies

Abstract : Non-volatile memories and flip-flops can improve the energy efficiency in battery-operated devices by eliminating the sleep-mode consumption, while maintaining the system state. Among emerging embedded NVM technologies, ReRAMs differentiate itself with a fast programming time, a simple CMOS-compatible structure and a good scalability. Previously proposed ReRAM-based non-volatile flip-flops (NVFF) have been implemented in 90nm or older CMOS nodes and suffer from CMOS reliability issues in scaled nodes due to high programming and forming voltages. This thesis makes the analysis of robust and reliable non-volatile design in 28nm CMOS node and below. It presents two novel thin-gate oxide CMOS design solutions for the programming of ReRAM devices. The programming circuits are applied in dual-voltage NVFF architecture which employs two ReRAM devices (2R). Alternative 1R NVFF architecture is also proposed in order to achieve higher density and lower consumption. With regard to the existing ReRAM technologies, given NVFF solutions are optimized for ReRAM programming conditions which improve endurance and minimize programming power. Statistical analysis of the FF core and its optimization was performed, to evaluate the best restore operation architectures which meet digital CMOS circuit design yield requirements. The NVFFs are implemented in 28nm CMOS FDSOI and benchmarked against a master slave flip-flop from a standard library and a data-retention flip-flop. Finally, to minimize the NVFF area overhead without impacting the robustness of \nv{} operations, multi-port non-volatile register file (NVRF) based on the 1R NVFF solution is proposed.
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Submitted on : Wednesday, June 22, 2022 - 12:25:41 PM
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  • HAL Id : tel-03701635, version 1


Natalija Jovanovic. Robust and reliable ReRAM-based non-volatile sequential logic circuits in deeply-scaled CMOS tehnologies. Micro and nanotechnologies/Microelectronics. Télécom ParisTech, 2016. English. ⟨NNT : 2016ENST0023⟩. ⟨tel-03701635⟩



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