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Mots clés

SoC Formal methods Confusion coefficient Security services DRAM Reliability Side-channel attacks Dynamic range Logic gates Masking countermeasure Aging MRAM Sécurité Fault injection Machine learning Voltage Asynchronous Loop PUF Field Programmable Gates Array FPGA Resistance Costs Switches Steadiness Image processing Differential Power Analysis DPA OCaml Mutual Information Analysis MIA Lightweight cryptography GSM CRT Fault injection attack Dual-rail with Precharge Logic DPL Side-channel attacks SCA Side-Channel Analysis Randomness Information leakage Side-channel attack Random access memory Robustness Countermeasures Energy consumption Variance-based Power Attack VPA Transistors Hardware Side-channel analysis Power-constant logic Filtering Routing Formal proof Circuit faults Masking AES Defect modeling Computational modeling Authentication Receivers ASIC Tunneling magnetoresistance SCA 3G mobile communication Magnetic tunnel junction Internet of Things Power demand PUF Magnetic tunneling STT-MRAM Security and privacy RSA Signal processing algorithms CPA Sensors Security Process variation Differential power analysis DPA Reverse engineering Convolution TRNG Intrusion detection Neural networks Writing FDSOI Linearity FPGA Side-Channel Analysis SCA Estimation Field programmable gate arrays Countermeasure Reverse-engineering Temperature sensors Elliptic curve cryptography Electromagnetic Cryptography Protocols Spin transfer torque Side-Channel Attacks Coq Hardware security Simulation Training Application-specific VLSI designs

 

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212

Références bibliographiques

428

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39 %

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